Datasheet Texas Instruments THS5651A — 数据表

制造商	Texas Instruments
系列	THS5651A

10位，125MSPS数模转换器（DAC）

数据表

PDF, 948 Kb, 修订版: A, 档案已发布: Sep 25, 2002

PDF, 948 Kb, 修订版: A, 档案已发布: Sep 25, 2002

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	THS5651AIDW	THS5651AIDWG4	THS5651AIDWR	THS5651AIPW	THS5651AIPWG4	THS5651AIPWR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes	Yes	Yes	No	No	No

	THS5651AIDW	THS5651AIDWG4	THS5651AIDWR	THS5651AIPW	THS5651AIPWG4	THS5651AIPWR
N	1	2	3	4	5	6
Pin	28	28	28	28	28	28
Package Type	DW	DW	DW	PW	PW	PW
Industry STD Term	SOIC	SOIC	SOIC	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	20	20	1000	50		2000
Carrier	TUBE	TUBE	LARGE T&R	TUBE		LARGE T&R
Device Marking	THS5651AI	THS5651AI	THS5651AI	TJ5651A		TJ5651A
Width (mm)	7.5	7.5	7.5	4.4	4.4	4.4
Length (mm)	17.9	17.9	17.9	9.7	9.7	9.7
Thickness (mm)	2.35	2.35	2.35	1	1	1
Pitch (mm)	1.27	1.27	1.27	.65	.65	.65
Max Height (mm)	2.65	2.65	2.65	1.2	1.2	1.2
Mechanical Data	下载	下载	下载	下载	下载	下载

Parameters / Models	THS5651AIDW	THS5651AIDWG4	THS5651AIDWR	THS5651AIPW	THS5651AIPWG4	THS5651AIPWR
Approx. Price (US$)		4.68 \| 1ku			4.68 \| 1ku
Architecture	Current Source	Current Source	Current Source	Current Source	Current Source	Current Source
DAC Channels	1		1	1	1	1
DAC: Channels		1
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS
Interpolation	1x		1x	1x	1x	1x
Operating Temperature Range, C	-40 to 85		-40 to 85	-40 to 85		-40 to 85
Operating Temperature Range(C)		-40 to 85			-40 to 85
Package Group	SOIC	SOIC	SOIC	TSSOP	TSSOP	TSSOP
Package Size(mm2=WxL)		28SOIC: 184 mm2: 10.3 x 17.9
Package Size: mm2:W x L, PKG	28SOIC: 184 mm2: 10.3 x 17.9(SOIC)		28SOIC: 184 mm2: 10.3 x 17.9(SOIC)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)		28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Package Size: mm2:W x L (PKG)					28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ), mW	175		175	175		175
Power Consumption(Typ)(mW)		175			175
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Resolution, Bits	10		10	10		10
Resolution(Bits)		10			10
SFDR, dB	61		61	61		61
SFDR(dB)		77			77
Sample / Update Rate, MSPS	125		125	125		125
Sample / Update Rate(MSPS)		125			125
Settling Time(?s)		0.035

	THS5651AIDW	THS5651AIDWG4	THS5651AIDWR	THS5651AIPW	THS5651AIPWG4	THS5651AIPWR
RoHS	Compliant	Compliant	Compliant	Compliant	Not Compliant	Compliant
Pb Free	Yes	No

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Wideband Complementary Current Output DAC Single-Ended Interface
PDF, 597 Kb, 档案已发布: Jun 21, 2005
High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
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Noise Analysis for High Speed Op Amps (Rev. A)
PDF, 256 Kb, 修订版: A, 档案已发布: Jan 17, 2005
As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

系列: THS5651A (6)

Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)