SLLS165G -JANUARY 1994 -REVISED MARCH 2006 D Integrated Asynchronous Communications
D
D
D D
D D
D Element
Consists of Four Improved TL16C550 ACEs
Plus Steering Logic
In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU
In TL16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
Programmable Baud Rate Generators
Which Allow Division of Any Input
Reference Clock by 1 to (216 - 1) and
Generate an Internal 16 Г— Clock …
