Datasheet Texas Instruments TLC2654 — 数据表

制造商	Texas Instruments
系列	TLC2654

低噪声斩波稳定的运算放大器

数据表

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PDF, 1.2 Mb, 修订版: G, 档案已发布: Apr 25, 2001

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价格

状态

	TLC2654C-14D	TLC2654C-14DR	TLC2654C-8D	TLC2654C-8DG4	TLC2654C-8DR	TLC2654C-8DRG4	TLC2654CN	TLC2654CP	TLC2654CPE4	TLC2654I-8D	TLC2654I-8DR	TLC2654IP	TLC2654IPE4	TLC2654Q-8D
Lifecycle Status	Obsolete (Manufacturer has discontinued the production of the device)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample Availability	Yes	No	Yes	No	No	No	No	No	No	No	No	No	No	No

打包

	TLC2654C-14D	TLC2654C-14DR	TLC2654C-8D	TLC2654C-8DG4	TLC2654C-8DR	TLC2654C-8DRG4	TLC2654CN	TLC2654CP	TLC2654CPE4	TLC2654I-8D	TLC2654I-8DR	TLC2654IP	TLC2654IPE4	TLC2654Q-8D
N	1	2	3	4	5	6	7	8	9	10	11	12	13	14
Pin	14	14	8	8	8	8	14	8	8	8	8	8	8	8
Package Type	D	D	D	D	D	D	N	P	P	D	D	P	P	D
Industry STD Term	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	PDIP	PDIP	PDIP	SOIC	SOIC	PDIP	PDIP	SOIC
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDIP-T	R-PDIP-T	R-PDIP-T	R-PDSO-G	R-PDSO-G	R-PDIP-T	R-PDIP-T	R-PDSO-G
Width (mm)	3.91	3.91	3.91	3.91	3.91	3.91	6.35	6.35	6.35	3.91	3.91	6.35	6.35	3.91
Length (mm)	8.65	8.65	4.9	4.9	4.9	4.9	19.3	9.81	9.81	4.9	4.9	9.81	9.81	4.9
Thickness (mm)	1.58	1.58	1.58	1.58	1.58	1.58	3.9	3.9	3.9	1.58	1.58	3.9	3.9	1.58
Pitch (mm)	1.27	1.27	1.27	1.27	1.27	1.27	2.54	2.54	2.54	1.27	1.27	2.54	2.54	1.27
Max Height (mm)	1.75	1.75	1.75	1.75	1.75	1.75	5.08	5.08	5.08	1.75	1.75	5.08	5.08	1.75
Mechanical Data	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载
Package QTY		2500	75	75	2500	2500	25	50	50	75	2500	50	50
Carrier		LARGE T&R	TUBE	TUBE	LARGE T&R	LARGE T&R	TUBE	TUBE	TUBE	TUBE	LARGE T&R	TUBE	TUBE
Device Marking		TLC2654C	2654C	2654C	2654C	2654C	TLC2654CN	TLC2654CP	TLC2654CP	2654I	2654I	TLC2654IP	TLC2654IP

参数化

Parameters / Models	TLC2654C-14D	TLC2654C-14DR	TLC2654C-8D	TLC2654C-8DG4	TLC2654C-8DR	TLC2654C-8DRG4	TLC2654CN	TLC2654CP	TLC2654CPE4	TLC2654I-8D	TLC2654I-8DR	TLC2654IP	TLC2654IPE4	TLC2654Q-8D
Additional Features	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift	Zero Drift
Approx. Price (US$)	1.78 \| 1ku													1.78 \| 1ku
Architecture	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
CMRR(Min), dB		105	105	105	105	105	105	105	105	105	105	105	105
CMRR(Min)(dB)	105													105
CMRR(Typ), dB		125	125	125	125	125	125	125	125	125	125	125	125
CMRR(Typ)(dB)	125													125
GBW(Typ), MHz		1.9	1.9	1.9	1.9	1.9	1.9	1.9	1.9	1.9	1.9	1.9	1.9
GBW(Typ)(MHz)	1.9													1.9
Input Bias Current(Max), pA		60	60	60	60	60	60	60	60	60	60	60	60
Input Bias Current(Max)(pA)	60													60
Iq per channel(Max), mA		2.4	2.4	2.4	2.4	2.4	2.4	2.4	2.4	2.4	2.4	2.4	2.4
Iq per channel(Max)(mA)	2.4													2.4
Iq per channel(Typ), mA		1.5	1.5	1.5	1.5	1.5	1.5	1.5	1.5	1.5	1.5	1.5	1.5
Iq per channel(Typ)(mA)	1.5													1.5
Number of Channels		1	1	1	1	1	1	1	1	1	1	1	1
Number of Channels(#)	1													1
Offset Drift(Typ), uV/C		0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01
Offset Drift(Typ)(uV/C)	0.01													0.01
Operating Temperature Range, C		-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70
Operating Temperature Range(C)	-40 to 85 0 to 70													-40 to 85 0 to 70
Output Current(Typ), mA		3	3	3	3	3	3	3	3	3	3	3	3
Output Current(Typ)(mA)	3													3
Package Group	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	PDIP	PDIP	PDIP	SOIC	SOIC	PDIP	PDIP	SOIC
Package Size: mm2:W x L, PKG		8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	See datasheet (PDIP)	See datasheet (PDIP)	See datasheet (PDIP)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	See datasheet (PDIP)	See datasheet (PDIP)
Package Size: mm2:W x L (PKG)	See datasheet (PDIP)													See datasheet (PDIP)
Rail-to-Rail	In to V- Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V- Out
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Slew Rate(Typ), V/us		2.8	2.8	2.8	2.8	2.8	2.8	2.8	2.8	2.8	2.8	2.8	2.8
Slew Rate(Typ)(V/us)	2.8													2.8
Total Supply Voltage(Max), +5V=5, +/-5V=10		16	16	16	16	16	16	16	16	16	16	16	16
Total Supply Voltage(Max)(+5V=5, +/-5V=10)	16													16
Total Supply Voltage(Min), +5V=5, +/-5V=10		4.6	4.6	4.6	4.6	4.6	4.6	4.6	4.6	4.6	4.6	4.6	4.6
Total Supply Voltage(Min)(+5V=5, +/-5V=10)	4.6													4.6
Vn at 1kHz(Typ), nV/rtHz		23	23	23	23	23	23	23	23	23	23	23	23
Vn at 1kHz(Typ)(nV/rtHz)	23													23
Vos (Offset Voltage @ 25C)(Max), mV		0.02	0.02	0.02	0.02	0.02	0.02	0.02	0.02	0.02	0.02	0.02	0.02
Vos (Offset Voltage @ 25C)(Max)(mV)	0.02													0.02

生态计划

	TLC2654C-14D	TLC2654C-14DR	TLC2654C-8D	TLC2654C-8DG4	TLC2654C-8DR	TLC2654C-8DRG4	TLC2654CN	TLC2654CP	TLC2654CPE4	TLC2654I-8D	TLC2654I-8DR	TLC2654IP	TLC2654IPE4	TLC2654Q-8D
RoHS	Not Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Not Compliant
Pb Free	Yes	Yes	No	No	Yes	Yes	Yes

应用须知

下载
DC Parameters: Input Offset Voltage
PDF, 295 Kb, 档案已发布: Mar 27, 2001
The input offset voltage, VIO, is a common dc parameter in operational amplifier (op amp) specifications. This report aims to familiarize the engineer by discussing the basics and modern aspects of VIO by providing a definition and a detailed explaination of causes of VIO for BJT, BiFET, and CMOS devices. Discussion centers around measurement techniques, data sheet specifications, and the effect o
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Choosing an ADC and Op Amp for Minimum Offset
PDF, 72 Kb, 档案已发布: Oct 28, 1999
Designing a mixed-signal circuit containing analog and digital components can be a challenge to the development engineer. Requirements such as a low single-polarity supply voltage and a high degree of precision may conflict, and make the choice of components and the best circuit design difficult. This report discusses problems that arise in using operational amplifiers (op amps) for signal conditi

模型线

系列: TLC2654 (14)

TLC2654C-14D TLC2654C-14DR TLC2654C-8D TLC2654C-8DG4 TLC2654C-8DR TLC2654C-8DRG4 TLC2654CN TLC2654CP TLC2654CPE4 TLC2654I-8D TLC2654I-8DR TLC2654IP TLC2654IPE4 TLC2654Q-8D

制造商分类

Semiconductors> Amplifiers> Operational Amplifiers (Op Amps)> Precision Op Amps