Datasheet Texas Instruments TLK10022CTR — 数据表

TLK10022
www.ti.com SLLSEE7 – NOVEMBER 2013 10Gbps DUAL-CHANNEL MULTI-RATE SERIAL LINK AGGREGATOR
Check for Samples: TLK10022 1 INTRODUCTION
1.1 Features 1 Automatic Digital Multiplexing/De-Multiplexing
of 4, 3, or 2 Independent Lower-Speed Gigabit
Serial Lines into a Single Higher-Speed Gigabit
Serial Line 4 x (0.25 to 2.5 Gbps) to 1 x (1 to 10 Gbps)
Multiplexing 3 x (0.5 to 3.33 Gbps) to 1x (1.5 to 10 Gbps) 2 x (0.5 to 5 Gbps) to 1 x (1 to 10 Gbps) 1 x (0.5 to 2.5 Gbps) to 1 x (0.5 to 2.5 Gbps) Programmable Per Channel Lane Switching Wide Data Rate Range for Multiple Application
Support Transmit De-Emphasis and Adaptive Receiver
Equalization on Both Low Speed and High
Speed Sides 8B/10B ENDEC Coding Support Raw (unencoded) Data Support 1.2 Core Supply 1V; I/O: 1.5V/1.8V Programmable High Speed
Scrambling/Descrambling Functions Improve
Serial Link Transition Density and Reduce
Spectral Peaks Superior Signal Integrity Performance Low Power Operation: < 800mW per Channel
(typ) Flexible Clocking Multi Drive Capability (SFP+, backplane, cable) Support for Programmable Lane Marker
Character Support for Programmable HS/LS 10-Bit
Alignment Character Wide Range of Built-in Test Patterns 144-pin, 13mmx13mm FCBGA Package Applications Gigabit Serial Link Aggregation Communications System Backplanes Machine Vision Video/Image Data Processing
2.5GBPS
2.5GBPS
2.5GBPS
2.5GBPS ASSP 1 ASSP 3 2.5GBPS
2.5GBPS
2.5GBPS …