TLK2201B
TLK2201BI www.ti.com SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008 ETHERNET TRANSCEIVERS 1 to 1.6 Gigabits Per Second (Gbps)
Serializer/Deserializer (TLK2201B) 1.2 to 1.6 Gigabits Per Second (Gbps)
Serializer/Deserializer (TLK2201BI) Low Power Consumption 150 mV, LOS = 1, valid input signal
If magnitude of RXP–RXN < 150 mV and >50 mV, LOS is undefined
If magnitude of RXP–RXN < 50 mV, LOS = 0, loss of signal MODESEL 15 I
P/D(1) Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface.
When low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected.
The default mode is the TBI. LOOPEN 19 I Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active. TCK 49 I Test clock. IEEE1149.1 (JTAG) JTDI 48 I Test data input. IEEE1149.1 (JTAG) JTDO 27 O Test data output. IEEE1149.1 (JTAG) JTRSTN 56 I
P/U(2) Reset signal. IEEE1149.1 (JTAG) JTMS 55 I
P/U(2) Test mode select. IEEE1149.1 (JTAG) ENABLE 28 I
P/U(2) When this terminal is low, the device is disabled for Iddq testing. RD0 -RD9, RBCn, TXP, and
TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally. PRBSEN 16 I
P/D(1) PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low. TEST (1)
(2)
4 P/D = Internal pulldown …
