Datasheet Texas Instruments TLV2542 — 数据表

制造商Texas Instruments
系列TLV2542
Datasheet Texas Instruments TLV2542

12位,200 kSPS ADC,串行输出,与TMS320兼容(最高10MHz),双通道自动扫频

数据表

2.7 V to 5.5 V Low-Power 12-Bit 140/200 KSPS, Serial Analog-To-Digital Converter datasheet
PDF, 1.2 Mb, 修订版: E, 档案已发布: Apr 12, 2010
从文件中提取

价格

状态

TLV2542CDGKTLV2542CDGKG4TLV2542CDGKRTLV2542IDTLV2542IDG4TLV2542IDGKTLV2542IDGKG4TLV2542IDGKRTLV2542IDR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoNoNoYesNoYesNoYes

打包

TLV2542CDGKTLV2542CDGKG4TLV2542CDGKRTLV2542IDTLV2542IDG4TLV2542IDGKTLV2542IDGKG4TLV2542IDGKRTLV2542IDR
N123456789
Pin888888888
Package TypeDGKDGKDGKDDDGKDGKDGKD
Industry STD TermVSSOPVSSOPVSSOPSOICSOICVSSOPVSSOPVSSOPSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY808025007575808025002500
CarrierTUBETUBELARGE T&RTUBETUBETUBETUBELARGE T&RLARGE T&R
Device MarkingAHBAHBAHB2542I2542IAHCAHCAHC2542I
Width (mm)3333.913.913333.91
Length (mm)3334.94.93334.9
Thickness (mm).97.97.971.581.58.97.97.971.58
Pitch (mm).65.65.651.271.27.65.65.651.27
Max Height (mm)1.071.071.071.751.751.071.071.071.75
Mechanical Data下载下载下载下载下载下载下载下载下载

参数化

Parameters / ModelsTLV2542CDGK
TLV2542CDGK
TLV2542CDGKG4
TLV2542CDGKG4
TLV2542CDGKR
TLV2542CDGKR
TLV2542ID
TLV2542ID
TLV2542IDG4
TLV2542IDG4
TLV2542IDGK
TLV2542IDGK
TLV2542IDGKG4
TLV2542IDGKG4
TLV2542IDGKR
TLV2542IDGKR
TLV2542IDR
TLV2542IDR
# Input Channels222222222
Analog Voltage AVDD(Max), V5.55.55.55.55.55.55.55.55.5
Analog Voltage AVDD(Min), V2.72.72.72.72.72.72.72.72.7
ArchitectureSARSARSARSARSARSARSARSARSAR
Digital Supply(Max), V5.55.55.55.55.55.55.55.55.5
Digital Supply(Min), V2.72.72.72.72.72.72.72.72.7
INL(Max), +/-LSB111111111
Input Range(Max), V5.55.55.55.55.55.55.55.55.5
Input TypeSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-Ended
Integrated FeaturesOscillatorOscillatorOscillatorOscillatorOscillatorOscillatorOscillatorOscillatorOscillator
InterfaceSPISPISPISPISPISPISPISPISPI
Multi-Channel ConfigurationMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexed
Operating Temperature Range, C-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70
Package GroupVSSOPVSSOPVSSOPSOICSOICVSSOPVSSOPVSSOPSOIC
Package Size: mm2:W x L, PKG8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8VSSOP: 15 mm2: 4.9 x 3(VSSOP)8SOIC: 29 mm2: 6 x 4.9(SOIC)
Power Consumption(Typ), mW2.82.82.82.82.82.82.82.82.8
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExtExtExtExt
Resolution, Bits121212121212121212
SINAD, dB727272727272727272
SNR, dB727272727272727272
Sample Rate (max), SPS200kSPS200kSPS200kSPS200kSPS200kSPS200kSPS200kSPS200kSPS200kSPS
Sample Rate(Max), MSPS0.20.20.20.20.20.20.20.20.2
THD(Typ), dB-84-84-84-84-84-84-84-84-84

生态计划

TLV2542CDGKTLV2542CDGKG4TLV2542CDGKRTLV2542IDTLV2542IDG4TLV2542IDGKTLV2542IDGKG4TLV2542IDGKRTLV2542IDR
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • Interfacing the TLC2552 and TLV2542 to the MSP430F149
    PDF, 123 Kb, 档案已发布: Feb 10, 2003
    This application note discusses the features of the TLC2552 and TLV2542 ADC. An SPI interface code example for the MSP430F149 to the TLC2552 ADC, and for the MSP430F149 to the TLV2542 ADC, are also presented.
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, 档案已发布: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)