Datasheet Texas Instruments TLV2772A — 数据表
| 制造商 | Texas Instruments |
| 系列 | TLV2772A |
双路2.7V高摆率轨至轨输出运算放大器
数据表
2.7-V High-Slew-Rate Rail-to-Rail Output Op Amps w/ Shutdown datasheet
PDF, 2.5 Mb, 修订版: G, 档案已发布: Feb 23, 2004
从文件中提取
价格
状态
| TLV2772AID | TLV2772AIDG4 | TLV2772AIDR | TLV2772AIDRG4 | TLV2772AIP | TLV2772AQPW | TLV2772AQPWR | |
|---|---|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No | No | No | No | No | Yes | No |
打包
| TLV2772AID | TLV2772AIDG4 | TLV2772AIDR | TLV2772AIDRG4 | TLV2772AIP | TLV2772AQPW | TLV2772AQPWR | |
|---|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| Pin | 8 | 8 | 8 | 8 | 8 | 8 | 8 |
| Package Type | D | D | D | D | P | PW | PW |
| Industry STD Term | SOIC | SOIC | SOIC | SOIC | PDIP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDIP-T | R-PDSO-G | R-PDSO-G |
| Package QTY | 75 | 75 | 2500 | 2500 | 50 | 150 | |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R | TUBE | SMALL T&R | |
| Device Marking | 2772AI | 2772AI | 2772AI | 2772AI | TLV2772AI | 2772AQ | |
| Width (mm) | 3.91 | 3.91 | 3.91 | 3.91 | 6.35 | 4.4 | 4.4 |
| Length (mm) | 4.9 | 4.9 | 4.9 | 4.9 | 9.81 | 3 | 3 |
| Thickness (mm) | 1.58 | 1.58 | 1.58 | 1.58 | 3.9 | 1 | 1 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 | 1.27 | 2.54 | .65 | .65 |
| Max Height (mm) | 1.75 | 1.75 | 1.75 | 1.75 | 5.08 | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | TLV2772AID | TLV2772AIDG4 | TLV2772AIDR | TLV2772AIDRG4 | TLV2772AIP | TLV2772AQPW | TLV2772AQPWR |
|---|---|---|---|---|---|---|---|
| Additional Features | N/A | N/A | N/A | N/A | N/A | N/A | N/A |
| Approx. Price (US$) | 1.11 | 1ku | ||||||
| Architecture | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS |
| CMRR(Min), dB | 60 | 60 | 60 | 60 | 60 | 60 | |
| CMRR(Min)(dB) | 60 | ||||||
| CMRR(Typ), dB | 96 | 96 | 96 | 96 | 96 | 96 | |
| CMRR(Typ)(dB) | 96 | ||||||
| GBW(Typ), MHz | 5.1 | 5.1 | 5.1 | 5.1 | 5.1 | 5.1 | |
| GBW(Typ)(MHz) | 5.1 | ||||||
| Input Bias Current(Max), pA | 60 | 60 | 60 | 60 | 60 | 60 | |
| Input Bias Current(Max)(pA) | 60 | ||||||
| Iq per channel(Max), mA | 2 | 2 | 2 | 2 | 2 | 2 | |
| Iq per channel(Max)(mA) | 2 | ||||||
| Iq per channel(Typ), mA | 1 | 1 | 1 | 1 | 1 | 1 | |
| Iq per channel(Typ)(mA) | 1 | ||||||
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 | |
| Number of Channels(#) | 2 | ||||||
| Offset Drift(Typ), uV/C | 2 | 2 | 2 | 2 | 2 | 2 | |
| Offset Drift(Typ)(uV/C) | 2 | ||||||
| Operating Temperature Range, C | -40 to 125 | -40 to 125 | -40 to 125 | -40 to 125 | -40 to 125 | -40 to 125 | |
| Operating Temperature Range(C) | -40 to 125 | ||||||
| Output Current(Typ), mA | 40 | 40 | 40 | 40 | 40 | 40 | |
| Output Current(Typ)(mA) | 40 | ||||||
| Package Group | SOIC | SOIC | SOIC | SOIC | PDIP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 8SOIC: 29 mm2: 6 x 4.9(SOIC) | 8SOIC: 29 mm2: 6 x 4.9(SOIC) | 8SOIC: 29 mm2: 6 x 4.9(SOIC) | 8SOIC: 29 mm2: 6 x 4.9(SOIC) | See datasheet (PDIP) | 8TSSOP: 19 mm2: 6.4 x 3(TSSOP) | |
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP) | ||||||
| Rail-to-Rail | In to V-,Out | In to V-,Out | In to V-,Out | In to V-,Out | In to V-,Out | In to V-,Out | In to V- Out |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
| Slew Rate(Typ), V/us | 10.5 | 10.5 | 10.5 | 10.5 | 10.5 | 10.5 | |
| Slew Rate(Typ)(V/us) | 10.5 | ||||||
| Total Supply Voltage(Max), +5V=5, +/-5V=10 | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 | |
| Total Supply Voltage(Max)(+5V=5, +/-5V=10) | 5.5 | ||||||
| Total Supply Voltage(Min), +5V=5, +/-5V=10 | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 | |
| Total Supply Voltage(Min)(+5V=5, +/-5V=10) | 2.5 | ||||||
| Vn at 1kHz(Typ), nV/rtHz | 17 | 17 | 17 | 17 | 17 | 17 | |
| Vn at 1kHz(Typ)(nV/rtHz) | 17 | ||||||
| Vos (Offset Voltage @ 25C)(Max), mV | 1.6 | 1.6 | 1.6 | 1.6 | 1.6 | 1.6 | |
| Vos (Offset Voltage @ 25C)(Max)(mV) | 1.6 |
生态计划
| TLV2772AID | TLV2772AIDG4 | TLV2772AIDR | TLV2772AIDRG4 | TLV2772AIP | TLV2772AQPW | TLV2772AQPWR | |
|---|---|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Not Compliant |
| Pb Free | Yes | No |
应用须知
- TLV277x/TLV277xA EMI Immunity PerformancePDF, 284 Kb, 档案已发布: Dec 20, 2012
- Use of Rail-to-Rail Operational Amplifiers (Rev. A)PDF, 159 Kb, 修订版: A, 档案已发布: Dec 22, 1999
This application report assists design engineers to understand the functionality and benefits of rail-to-rail operational amplifiers. It shows simplified schematics, functions, and characteristics of the input and output stages. Typical application schematics for rail-to-rail operational amplifiers are also discussed.
模型线
系列: TLV2772A (7)
制造商分类
- Semiconductors> Amplifiers> Operational Amplifiers (Op Amps)> Precision Op Amps