Datasheet Texas Instruments TMS320C6455 — 数据表

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应用须知

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  Implementing Serial Rapid I/O PCB layout on a TMS320C6455 Hardware Design (Rev. A)
  PDF, 127 Kb, 修订版: A, 档案已发布: Aug 17, 2006
  This application report contains implementation instructions for the Serial Rapid I/O (SRIO) interface on the TMS320C6455 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previous approaches for other interfaces.Serial Rapid I/O is an industry-standard high-speed switched-packet interconnect. Physical layer data t
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  SW Operation of Gigabit Ethernet Media Access Controller on TMS320C645x DSP
  PDF, 288 Kb, 档案已发布: Oct 31, 2006
  The TMS645x devices provide an efficient interface between the DSP core processor and the network via a high performance Gigabit Ethernet Media Access Controller (EMAC), supporting four Media Independent Interfaces to the physical layer device (PHY).This application report discusses the software interface used to operate the EMAC and Management Data Input/Output (MDIO) modules. It describes i
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  Implementing DDR2 PCB Layout on the TMS320C6455/C6454 (Rev. E)
  PDF, 158 Kb, 修订版: E, 档案已发布: Jul 8, 2008
  This application report contains implementation instructions for the DDR2 interface contained on the TMS320C6454/5 digital signal processor (DSP) device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.The previous approach specified device timing in terms of data sheet specifications and simulation models. The system designer was
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  TMS320C6455/C6454 Power Consumption Summary (Rev. B)
  PDF, 75 Kb, 修订版: B, 档案已发布: Oct 1, 2007
  This application report discusses the power consumption of the Texas Instruments TMS320C6455 and TMS320C6454 digital signal processor (DSPs). The power consumption on the C645x devices is highly application-dependent, therefore, a power spreadsheet that predicts power consumption is provided along with this application note. The power spreadsheet can be used for the purpose of modeling power consu
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  Preparing an C645x application for I2C Boot Load
  PDF, 85 Kb, 档案已发布: Sep 5, 2006
  This application report describes how to prepare a C645x application for the I2C boot load process.The enclosed .zip archive contains all utilities and examples necessary to build a test application, program it into DSK6455's I2C ROM, change the boot mode to I2C boot load, and verify that the test application has been loaded from the I2C and is running correctly.
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  EDMA v3.0 (EDMA3) Migration Guide for TMS320C645x DSP
  PDF, 343 Kb, 档案已发布: Dec 23, 2005
  The TMS320C645x devices introduce a newly designed Enhanced Direct Memory Access (EDMA3). The EDMA3 has many new features that improve system performance and enhance debugging capabilities. This document summarizes the key differences between EDMA3 on the TMS320C645x devices and EDMA2 on the TMS320C64x devices. This document also provides guidance for migrating from EDMA2 to EDMA3.
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  TMS320C6455 to TMS320C6474 Migration Guide
  PDF, 311 Kb, 档案已发布: Oct 14, 2008
  The TMS320C6455 fixed-point digital signal processor (DSP) and the TMS320C6474 communications infrastructure DSP are two of Texas Instruments’ high-performance DSP processors, each offering high-speed DSP processing, large internal memories, a rich set of peripherals, and other support functions useful in a system environment.This application report describes device considerations for migrati
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  TMS320C6455 Design Guide and Comparisons to TMS320C6416T (Rev. A)
  PDF, 369 Kb, 修订版: A, 档案已发布: Sep 8, 2009
  This document describes system design considerations for the TMS320C6455 (C6455). It also gives comparisons to designing with the TMS320C6416T (C6416T) for those familiar with that device. The objective of this document is to cover system design considerations for the C6455. Those familiar with the C6416T can use the comparisons to migrate a C6416T design to the C6455. In some cases there is infor
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  TMS320C64x+ Megamodule
  PDF, 122 Kb, 档案已发布: Nov 16, 2004
  The C64X+ Megamodule supports a wide variety of internal memory configurations by allowing the L1 program and data memory (L1P and L1D) to set as cache only, SRAM only, or a mixture of cache and SRAM. In addition, the C64x+ Megamodule provides new system functionality including: cache freeze, Internal DMA (IDMA), bandwidth management, and memory protection. This document discusses the enhancements
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  Ultrasound Scan Conversion on TI's C64x+ DSPs
  PDF, 656 Kb, 档案已发布: Apr 3, 2009
  One of the recent significant developments in ultrasound is the emergence of portable and handheld ultrasound machines and their rapid acceptance in the market place.Because of their power efficiency and high performance digital signal processor (DSP) based devices have been increasingly used as the main processing engine in these portable and hand carried units.

  This application report dis

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  Tuning VCP2 and TCP2 Bit Error Rate Performance
  PDF, 293 Kb, 档案已发布: Feb 11, 2011
  In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
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  Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)
  PDF, 80 Kb, 修订版: A, 档案已发布: Jul 19, 2013
  This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
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  EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (Rev. A)
  PDF, 292 Kb, 修订版: A, 档案已发布: Aug 21, 2008
  This application report summarizes the key differences between the enhanced direct memory access (EDMA3) used on C64x+в„ў DSP devices and the EDMA2 used on TMS320C64xв„ў DSP devices, and provides guidance for migrating from EDMA2 to EDMA3.
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  Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A)
  PDF, 93 Kb, 修订版: A, 档案已发布: Jul 17, 2008
  This application report motivates the way the DDR high-speed timing requirements are now going to be communicated to system designers. The traditional method of using data sheet parameters and simulation models is tedious. The system designer uses this information to evaluate whether timing specifications are met and can be expected to operate reliably.Ultimately, the real question the hardwa
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  TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
  PDF, 310 Kb, 修订版: A, 档案已发布: Oct 20, 2005
  This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
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  Common Object File Format (COFF)
  PDF, 125 Kb, 档案已发布: Apr 15, 2009
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  Introduction to TMS320C6000 DSP Optimization
  PDF, 535 Kb, 档案已发布: Oct 6, 2011
  The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

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• Semiconductors> Processors> Digital Signal Processors> C6000 DSP> Other C6000 DSP