Datasheet Texas Instruments TMS320C6670 — 数据表

制造商	Texas Instruments
系列	TMS320C6670

数据表

价格

状态

打包

参数化

Parameters / Models	TMS320C6670ACYP2	TMS320C6670ACYPA	TMS320C6670ACYPA2	TMS320C6670AXCYP	TMS320C6670AXCYP2	TMS320C6670AXCYPA	TMS320C6670AXCYPA2	TMS320C6670CYP	TMS320C6670CYP2	TMS320C6670CYPA	TMS320C6670CYPA2	TMS320C6670XCPY2	TMS320C6670XCYP	TMS320C6670XCYPA	TMS320C6670XCYPA2	TMX320C6670AXCYP	TMX320C6670CYP
Applications	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom	Communications and Telecom
Approx. Price (US$)								168.00 | 1ku	168.00 | 1ku			168.00 | 1ku				168.00 | 1ku	168.00 | 1ku
DRAM	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3	DDR3
DSP	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x	4 C66x
DSP MHz, Max.	1000,1200	1000,1200	1000,1200	1000,1200	1000,1200	1000,1200	1000,1200			1000,1200	1000,1200		1000,1200	1000,1200	1000,1200
DSP MHz (Max.)								1000 1200	1000 1200			1000 1200				1000 1200	1000 1200
EMAC	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000	10/100/1000
GFLOPS	64,76.8	64,76.8	64,76.8	64,76.8	64,76.8	64,76.8	64,76.8	64 76.8	64 76.8	64,76.8	64,76.8	64 76.8	64,76.8	64,76.8	64,76.8	64 76.8	64 76.8
Hardware Accelerators	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2 TCP3d TCP3e FFT Coprocessor	VCP2 TCP3d TCP3e FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2 TCP3d TCP3e FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2,TCP3d,TCP3e,FFT Coprocessor	VCP2 TCP3d TCP3e FFT Coprocessor	VCP2 TCP3d TCP3e FFT Coprocessor
On-Chip L2 Cache	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB	4096 KB
Operating Temperature Range, C	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85			-40 to 100,0 to 85	-40 to 100,0 to 85		-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85
Operating Temperature Range(C)								-40 to 100 0 to 85	-40 to 100 0 to 85			-40 to 100 0 to 85				-40 to 100 0 to 85	-40 to 100 0 to 85
Other On-Chip Memory	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB	2048 KB
PCI/PCIe	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2
Package Size: mm2:W x L, PKG	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)			See datasheet (FCBGA)	See datasheet (FCBGA)		See datasheet (FCBGA)	See datasheet (FCBGA)	See datasheet (FCBGA)
Package Size: mm2:W x L (PKG)								See datasheet (FCBGA)	See datasheet (FCBGA)			See datasheet (FCBGA)				See datasheet (FCBGA)	See datasheet (FCBGA)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Serial I/O	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2 I2C RapidIO SPI UART	AIF2 I2C RapidIO SPI UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2 I2C RapidIO SPI UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2,I2C,RapidIO,SPI,UART	AIF2 I2C RapidIO SPI UART	AIF2 I2C RapidIO SPI UART
Serial RapidIO	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)	1 (four lanes)
Total On-Chip Memory, KB	6528	6528	6528	6528	6528	6528	6528			6528	6528		6528	6528	6528
Total On-Chip Memory (KB)								6528	6528			6528				6528	6528

生态计划

应用须知

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  AIF1-to-AIF2 Antenna Interface Migration Guide for KeyStone Devices
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  Connecting AIF to FFTC Guide for KeyStone Devices
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  Keystone NDK FAQ
  PDF, 54 Kb, 档案已发布: Oct 3, 2016
  This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices.
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  TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
  PDF, 3.2 Mb, 档案已发布: Oct 9, 2014
  This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
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  TI Keystone DSP PCIe SerDes IBIS-AMI Models
  PDF, 4.8 Mb, 档案已发布: Oct 9, 2014
  This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
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  SerDes Implementation Guidelines for KeyStone I Devices
  PDF, 590 Kb, 档案已发布: Oct 31, 2012
  The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
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  KeyStone I DDR3 Initialization (Rev. E)
  PDF, 114 Kb, 修订版: E, 档案已发布: Oct 28, 2016
  The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
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  TMS320C66x DSP Generation of Devices (Rev. A)
  PDF, 245 Kb, 修订版: A, 档案已发布: Apr 25, 2011
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  Hardware Design Guide for KeyStone Devices (Rev. C)
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  Tuning VCP2 and TCP2 Bit Error Rate Performance
  PDF, 293 Kb, 档案已发布: Feb 11, 2011
  In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
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  SERDES Link Commissioning on KeyStone I and II Devices
  PDF, 138 Kb, 档案已发布: Apr 13, 2016
  The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
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  PCIe Use Cases for KeyStone Devices
  PDF, 320 Kb, 档案已发布: Dec 13, 2011
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  The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
  PDF, 20 Kb, 修订版: A, 档案已发布: Nov 10, 2010
  The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
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  Optimizing Loops on the C66x DSP
  PDF, 585 Kb, 档案已发布: Nov 9, 2010
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  Clocking Design Guide for KeyStone Devices
  PDF, 1.5 Mb, 档案已发布: Nov 9, 2010
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  DDR3 Design Requirements for KeyStone Devices (Rev. B)
  PDF, 582 Kb, 修订版: B, 档案已发布: Jun 5, 2014
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  Multicore Programming Guide (Rev. B)
  PDF, 1.8 Mb, 修订版: B, 档案已发布: Aug 29, 2012
  As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
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  Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
  PDF, 324 Kb, 修订版: A, 档案已发布: Aug 17, 2016
  This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

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制造商分类

• Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP