Datasheet Texas Instruments TMS320TCI100 — 数据表
| 制造商 | Texas Instruments |
| 系列 | TMS320TCI100 |
定点数字信号处理器
数据表
价格
状态
| TMS320TCI100 | TMS320TCI100GLZ | TMX320TCI100BCLZ7 | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No | No | No |
打包
| TMS320TCI100 | TMS320TCI100GLZ | TMX320TCI100BCLZ7 | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 532 | ||
| Package Type | CLZ | ||
| Industry STD Term | FC/CSP | ||
| JEDEC Code | S-PBGA-N | ||
| Width (mm) | 23 | ||
| Length (mm) | 23 | ||
| Thickness (mm) | 2.61 | ||
| Pitch (mm) | .8 | ||
| Max Height (mm) | 3.25 | ||
| Mechanical Data | 下载 |
生态计划
| TMS320TCI100 | TMS320TCI100GLZ | TMX320TCI100BCLZ7 | |
|---|---|---|---|
| RoHS | Not Compliant | Not Compliant | Not Compliant |
| Pb Free | No | No | No |
应用须知
- TMS320TCI100 Power Sequencing Requirements (Rev. B)PDF, 128 Kb, 修订版: B, 档案已发布: Feb 21, 2008
This application report describes the power sequencing requirements for all TCI100 devices with respect to the dependencies associated with reset, clock, and signal pins during power up. It also explains what to avoid and potential issues associated with power-up sequencing with respect to the external memory interface (EMIF) peripheral. - TMS320C6000 DSP Multiprocessing With a Crossbar SwitchPDF, 140 Kb, 档案已发布: Feb 16, 2001
Current generations of telemcommunications infrastructure require intensive real-time computation. To meet the demands of next generation equipment, such as 3G wireless base stations, designers must seek methods to improve hardware and software efficiency.These real-time systems are typically distributed systems consisting of one master processor and one or more slave processors. Software flex - External Programming of the TMS320C64x EDMA for Low Overhead Data TransfersPDF, 118 Kb, 档案已发布: Jul 16, 2004
This application report details a mechanism by which an external slave device can directly initiate direct memory access (DMA) transfers with a TMS320C64xв„ў digital signal processor (DSP) without processor intervention. The mechanism utilizes the RAM-based architecture of the TMS320C64x enhanced direct memory access (EDMA) controller, static DMA transfers and DMA chaining to effectively a - How to Calculate the Period Jitter from the SSCR for High-Speed ADCsPDF, 218 Kb, 档案已发布: Dec 17, 2003
This document introduces a general formula to translate the phase noise of a clock source, rated via the Single Sideband to Carrier Ratio, to the cycle-to-cycle jitter of the oscillation period. The link allows to seamlessly aggregate the external clock source phase noise, usually given in dBc/Hz, to the phase stability figure of the on-chip clock synchronization circuitry, usually rated in ps-RMS - TMS320TCI6482 Design Guide and Comparisons to TMS320TCI100 (Rev. B)PDF, 3.2 Mb, 修订版: B, 档案已发布: Apr 25, 2006
This document describes system design considerations for the TMS320TCI6482 (TCI6482). It also gives comparisons to designing with the TMS320TCI100 (TCI100) for those familiar with that device. The objective of this document is to cover system design considerations for the TCI6482. Those familiar with the TCI100 can use the comparisons to migrate a TCI100 design to the TCI6482. In some cases there - Migrating from TMS320C6416 to TMS320TCI100 (Rev. A)PDF, 69 Kb, 修订版: A, 档案已发布: Aug 15, 2003
This application report describes issues of interest related to migration from the TMS320C6416 to the TMS320TCI100 device. The objective of this document is to indicate differences between the two devices. Functions that are identical between the two devices are not included. For detailed information on the specific functions of either device, refer to the TMS320C6414, TMS320C6415, TMS320C6416 Fix
模型线
系列: TMS320TCI100 (3)
制造商分类
- Semiconductors> Processors> Other Processors