Datasheet Analog Devices ADA4062-2ACPZ-RL — 数据表

Low Power JFET-Input Op Amps
ADA4062-2/ADA4062-4
PIN CONFIGURATIONS Low input bias current: 50 pA maximum
Offset voltage
1.5 mV maximum for B grade (ADA4062-2 SOIC package)
2.5 mV maximum for A grade
Offset voltage drift: 5 μV/°C typical
Slew rate: 3.3 V/μs typical
CMRR: 90 dB typical
Low supply current: 165 μA typical
High input impedance
Unity-gain stable
±5 V to ±15 V dual-supply operation
Packaging
8-lead SOIC, 8-lead MSOP, 10-lead LFCSP, 14-lead TSSOP, and
16-lead LFCSP packages OUT A 1
–IN A 2 ADA4062-2 +IN A 3 TOP VIEW
(Not to Scale) V– 4 OUT B 6 –IN B 5 +IN B 9 V+ 1 OUT A 10 NC 8 OUT B –IN A 2 ADA4062-2 07670-065 +IN B 6 NC 5 NC = NO CONNECT V– 4 7 –IN B
TOP VIEW
(Not to Scale) +IN A 3 GENERAL DESCRIPTION OUT A 1 14 OUT D –IN A 2 13 –IN D +IN A 3 ADA4062-4 12 +IN D V+ 4 TOP VIEW
(Not to Scale) 11 V– +IN B 5 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C 07670-064 Figure 2. 10-Lead LFCSP Power controls and monitoring
Active filters
Industrial/process controls …