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  A Collection of Differential to Single-Ended Signal Conditioning Circuits for Use with the LTC2400, a 24-Bit No Latency Delta Sigma ADC in an SO-8 &mdash AN78
  PDF, 177 Kb, 档案已发布: Aug 7, 1999
  This application note describes six low power differential-tosingle- ended signal conditioning circuits for the LTC2400 No Latency ΔΣTM 24-bit ADC. These circuits offer the customer a number of choices for conditioning differential input signals as low as 5mV to as high as ±2.5V, as well as operation on a single 5V or ±5V supplies. Each circuit description also covers circuit design and implementation techniques that can help preserve the LTC2400's inherently high effective resolution. AN78 concludes with two circuits for digitizing temperature when using an RTD or Type S thermocouple.
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  Application Note 78
  August 1999
  A Collection of Differential to Single-Ended Signal Conditioning
  Circuits for Use with the LTC2400, a 24-Bit No Latency ∆Σ ADC
  in an SO-8
  By Kevin R. Hoskins and Derek V. Redmayne
  INTRODUCTION
  The LTC®2400 is the industry’s first No Latency ∆ΣTM ADC
  that combines automatic offset and full-scale calibration,
  an internal oscillator, a sinc4 digital filter, and serial I/O to
  yield a 24-bit ADC with 1.5ВµVRMS input noise and singleshot conversion time architecture. It is the ideal
  A/D converter for temperature measurement and high
  effective resolution instrumentation applications, such as
  digital multimeters.
  This application note contains six circuits that
  extend the LTC2400’s capabilities using a number of low power differential-to-single-ended signal conditioning circuits. These circuits offer the customer a number of
  choices for conditioning differential input signals as low as
  5mV to as high as В±2.5V, as well as operation on a single
  5V or В±5V supplies. In each case, careful circuit design and
  implementation techniques were used to maintain or preserve the LTC2400’s inherently high effective resolution.
  In some cases, circuit accuracies (uncalibrated) exceed
  17 bits.
  , LTC and LT are registered trademarks of Linear Technology Corporation. …

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  How to Use the Worlds Smallest 24-Bit No Latency Delta-Sigma ADC to its Fullest Potential &mdash AN80
  PDF, 81 Kb, 档案已发布: Jul 1, 1999
  Linear Technology's LTC2400 is the world's first 24-bit ADC in an SO-8 package. An innovative new delta-sigma architecture has been developed. The result is a small, highly accurate, simple-to-use delta-sigma ADC. This Application Note was created to educate users on several topics associated with delta-sigma converters and to dispel confusion associated with this new oneshot, or No Latency ΔΣTM architecture. The key topics addressed include speed, noise, PGAs line frequency rejection, input current, multiplexing, analog input range and key features differentiating the LTC2400 from other delta-sigma ADCs.
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  Application Note 80
  July 1999 How to Use the World’s Smallest 24-Bit
  No Latency Delta-SigmaTM ADC to its Fullest Potential
  Frequently Asked Questions About Delta-Sigma ADCs and the LTC2400
  By Michael K. Mayes Linear Technology’s LTC®2400 is the world’s first 24-bit
  ADC in an SO-8 Package. An innovative new delta-sigma
  architecture has been developed. The result is a small,
  highly accurate, simple-to-use delta-sigma ADC. This
  paper was created to educate users on several topics
  associated with delta-sigma converters and to dispel
  confusion associated with this new one-shot, or No Latency ∆ΣTM, architecture. The key topics addressed here
  include speed, noise, PGAs, line frequency, rejection,
  input current, multiplexing, analog input range and key
  features differentiating the LTC2400 from other deltasigma ADCs.
  , LTC and LT are registered trademarks of Linear Technology Corporation.
  No Latency Delta-Sigma and No Latency ∆Σ are trademarks of Linear Technology Corporation. AN80-1 Application Note 80
  LTC2400 FREQUENTLY ASKED QUESTIONS
  I. Questions Dealing with Speed 1. I currently use a competitor’s delta sigma running at an
  output rate of 60Hz; can I run the LTC2400 at 60Hz? Additionally, the competitors’ part does not reject
  50Hz/60Hz. Competition: For a 60Hz notch, most of the competition’s
  output rates are 60Hz. However, 3 out of 4 output data are
  redundant; therefore these results can be thrown away.
  This, combined with the overhead of calibration and filter …

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  A Standards Lab Grade 20-Bit DAC with 0.1ppm/В° Drift: The Dedicated Art of Digitizing One Part Per Million &mdash AN86
  PDF, 540 Kb, 档案已发布: Jan 1, 2001
  This publication details a true 1ppm D-to-A converter. Total DC error of this processor corrected DAC remains within 1ppm from 18-32°C, including reference drift. DAC error exclusive of reference drift is substantially better. Construction details and performance verification techniques are included, along with a complete software listing.
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  Application Note 86
  January 2001
  A Standards Lab Grade 20-Bit DAC with 0.1ppm/В°C Drift
  The Dedicated Art of Digitizing One Part Per Million
  Jim Williams
  J. Brubaker
  P. Copley
  J. Guerrero
  F. Oprescu INTRODUCTION
  Significant progress in high precision, instrumentation
  grade D-to-A conversion has recently occurred. Ten years
  ago 12-bit D-to-A converters (DACs) were considered
  premium devices. Today, 16-bit DACs are available and
  increasingly common in system design. These are true
  precision devices with less than 1LSB linearity error and
  1ppm/В°C drift.1 Nonetheless, there are DAC applications
  that require even higher performance. Automatic test
  equipment, instruments, calibration apparatus, laser trimmers, medical electronics and other applications often
  require DAC accuracy beyond 16 bits. 18-bit DACs have
  been produced in circuit assembly form, although they are
  expensive and require frequent calibration. 20 and even
  23+ (0.1ppm!) bit DACs are represented by manually
  switched Kelvin-Varley dividers. These devices, although …

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  Delta Sigma ADC Bridge Measurement Techniques &mdash AN96
  PDF, 232 Kb, 档案已发布: Jan 17, 2005
  AN96 features several applications that demonstrate how to take full advantage of Linear Technology's delta sigma ADCs when interfacing to sensors. In many cases, signal conditioning can be greatly simplified or eliminated completely. This note explains where it is appropriate to use amplifiers and how to optimize amplifier gain. Also included are discussions on measuring effective number of bits (ENOB) and the relationship to instrument performance, frequency response of delta sigma ADCs, and test techniques. C source code for all of the applications is included to aid firmware development.
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  Application Note 96
  January 2005
  Delta Sigma ADC Bridge Measurement Techniques
  Mark Thoren
  Introduction In a typical 12-bit measurement system, the signal conditioning amplifier requires a very high gain in order to make
  use of the full ADC input range. A sensor with a 10mV fullscale output requires a gain of 500 to use the full input
  range of a typical 5V input ADC. A filter may be required to
  reduce noise at the expense of settling time. Additional
  difficulties arise when dealing with the large common
  mode voltage typical of a bridge sensor. Most instrumentation amplifiers have a large discrepancy between the
  typical CMRR and guaranteed minimum, which may require an additional trim. Sensors for pressure, load, temperature, acceleration and
  many other physical quantities often take the form of a
  Wheatstone bridge. These sensors can be extremely linear
  and stable over time and temperature. However, most
  things in nature are only linear if you don’t bend them too
  much. In the case of a load cell, Hooke’s law states that the
  strain in a material is proportional to the applied stress—
  as long as the stress is nowhere near the material’s yield
  point (the “point of no return” where the material is
  permanently deformed). The consequence is that a load
  cell based on a resistance strain gauge will have a very
  small electrical output—often only a few millivolts. In
  spite of this, instruments with 100,000 counts of resolution and more are possible. This Application Note presents …

设计须知

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  Testing Linearity of the LTC2400 24-Bit No Latency Delta SigmaTM A/D Converter Help from the Nineteenth Century &mdash Design Solutions 11
  PDF, 51 Kb, 档案已发布: Nov 1, 1999
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  Design Solutions 11
  November 1999
  Testing Linearity of the LTC2400 24-Bit No Latency ∆ΣTM
  A/D Converter
  Help from the Nineteenth Century
  by Jim Williams
  Introduction
  Verifying the linearity of the LTC2400 analog to digital
  converter requires special considerations. Typical
  nonlinearity is only 2ppm (0.0002%). Bench testing this
  necessitates some form of voltage source that produces
  equal amplitude output steps for incremental digital inputs. Additionally, for measurement confidence, it is desirable that the source be substantially more linear than
  the 2ppm requirement. This is, of course, a stringent
  demand and painfully close to the state of the art. follower is required to unload the KVD without introducing
  significant loading error. Now, our KVD looks like Figure 3.
  10k 2k 400Ω 80Ω INPUT The most linear “D to A” converter is also one of the oldest:
  Lord Kelvin’s Kelvin-Varley divider (KVD), in its most
  developed form, is linear to 0.1ppm. This manually switched
  device features ten million individual dial settings arranged in seven decades. It may be thought of as a
  3-terminal potentiometer with fixed “end-to-end” resistance and a 7-decade switched wiper position (Figure 1). R = 100k 80Ω
  OUT
  80Ω SEVEN-DECADE SWITCHED
  WIPER POSITION PERMITS …

文章

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  1- and 2-Channel, No Latency Delta Sigma , 24-Bit ADCs Easily Digitize a Variety of Sensors &mdash LT Journal
  PDF, 209 Kb, 档案已发布: Feb 1, 2000
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  LINEAR TECHNOLOGY
  FEBRUARY 2000 IN THIS ISSUE…
  COVER ARTICLE
  1-and 2-Channel, No Latency ∆Σ,
  24-Bit ADCs Easily Digitize a
  Variety of Sensors . 1
  Michael K. Mayes and Derek Redmayne Issue Highlights . 2
  LTC® in the News… . 2
  DESIGN FEATURES
  Tiny SOT-23 Step-Down Regulator
  Switches at 1MHz for SpaceCritical Applications . 5 VOLUME X NUMBER 1 1-and 2-Channel,
  No Latency ∆Σ
  ∆Σ, 24-Bit
  ADCs Easily Digitize
  a Variety of Sensors
  by Michael K. Mayes
  and Derek Redmayne Damon Lee 10ВµA Quiescent Current Step-Down
  Regulator Extends Standby Time
  in Handheld Electronics . 8
  Greg Dittmer Beware: Worst-Case Specifications
  Can Be a Reality . 10
  Steve Hobrecht 400MHz Current Feedback Amps
  Offer High Slew Rate without the …

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  LTC2400 Differential Bridge Digitizers &mdash LT Journal
  PDF, 120 Kb, 档案已发布: Jun 1, 1999
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  DESIGN IDEAS LTC2400 Differential Bridge Digitizers
  by Kevin R. Hoskins and Derek Redmayne
  Both circuits combine an LTC1043
  precision switched capacitor block and
  an LTC1050 chopper stabilized op amp,
  creating a differential input, singleended output bridge amplifier that has
  a rail-to-rail common mode input
  range. The LTC1043 samples a differential input voltage, holds it on CS and
  transfers it to a ground-referred capacitor, CH. The voltage on CH is applied
  to the LTC1050’s noninverting input
  and amplified by the gain set by resistors R1 and R2 (101 for the values
  shown). The amplifier’s output is then
  converted to a digital value by the
  LTC2400.
  The LTC1043 achieves its best differential to single-ended conversion
  when its internal switching frequency
  is set by a 0.01ВµF capacitor, C1, and
  when 1ВµF capacitors are used for CS
  and CH. Using any other value will
  compromise the accuracy. For
  example, a C1 value of 0.1µF will typically increase the circuit’s overall
  nonlinearity tenfold. CS and CH should
  be a film type such as mylar or polypropylene. Conversion accuracy is …

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  No Latency Delta-Sigma ADC Techniques for Optimized Performance &mdash LT Journal
  PDF, 239 Kb, 档案已发布: May 1, 2001
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  DESIGN FEATURES Introduction Product Family Overview Linear Technology’s Delta-Sigma analog-to-digital converter product family
  simplifies a variety of applications.
  The products’ ease-of-use and high
  accuracy without the need for calibration, external clocks or complex
  interfaces enables designers to rethink
  their system architectures.
  Although 24 bits may seem excessive to some, many designers find
  significant advantages with these
  higher resolution converters. One
  such advantage is the elimination of
  front-end amplification. This enables
  direct digitization of many sensors
  while removing problems associated
  with front-end offset and gain errors
  as well as simplifying tare adjustments. One misconception commonly
  solved by designers using the
  LTC2400 family is the relationship
  between speed and resolution. Many
  designers have found that higher
  speed ADCs with averaging do not
  meet the one-shot performance of the
  LTC2400 family. The absolute accuracy of the LTC2400 family is
  demonstrated using a bridge sensor …

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  World &mdash LT Journal
  PDF, 417 Kb, 档案已发布: Nov 1, 1998
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  LINEAR TECHNOLOGY
  NOVEMBER 1998 IN THIS ISSUE…
  COVER ARTICLE
  World’s Smallest 24-Bit ADC Packs
  High Accuracy, Ease of Use, into SO-8
  . 1
  Michael K. Mayes Issue Highlights . 2 VOLUME VIII NUMBER 4 World’s Smallest 24-Bit ADC
  Packs High Accuracy,
  Ease of Use, into SO-8 LTCВ® in the News . 2
  DESIGN FEATURES
  Wide Input Range,
  High Efficiency Step-Down
  Switching Regulators . 5
  Jeff Schenkel A 4.5ns, 4mA, Single-Supply,
  Dual Comparator Optimized for
  3V/5V Operation . 10
  Joseph G. Petrofsky 250MHz RGB Video Multiplexer in
  Space-Saving Package Drives Cables,
  Switches Pixels at 100MHz . 16
  John Wright and Frank Cox LT В®1468: An Operational Amplifier
  for Fast, 16-Bit Systems . 18
  George Feliz LTC1622: Low Input Voltage, Current
  Mode PWM Buck Converter . 21 …

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• Data Conversion > Analog-to-Digital Converters (ADC) > Precision ADCs (Fs < 10Msps) > Single Channel ADCs