Datasheet Linear Technology LTM9001-AD — 数据表
| 制造商 | Linear Technology |
| 系列 | LTM9001-AD |
B-16位IF /基带接收器子系统
数据表
LTM9001-Ax/LTM9001-Bx - 16-Bit IF/Baseband Receiver Subsystem
PDF, 875 Kb, 修订版: C, 文件上传: Aug 21, 2017
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| LTM9001CV-AD#PBF | LTM9001IV-AD#PBF | |
|---|---|---|
| N | 1 | 2 |
| Package | 11.25mm × 11.25mm × 2.32mm LGA 包装外形图 | 11.25mm × 11.25mm × 2.32mm LGA 包装外形图 |
| Package Code | LGA | LGA |
| Package Index | 05-08-1809 | 05-08-1809 |
| Pin Count | 81 | 81 |
参数化
| Parameters / Models | LTM9001CV-AD#PBF | LTM9001IV-AD#PBF |
|---|---|---|
| ADCs | 1 | 1 |
| Architecture | Pipeline | Pipeline |
| Bits, bits | 16 | 16 |
| Number of Channels | 1 | 1 |
| DNL, LSB | 0.3 | 0.3 |
| Demo Boards | DC1241B-AA,DC1241B-AD,DC1241B-BA,DC1250A-AA,DC1250A-AD,DC1250A-BA | DC1241B-AA,DC1241B-AD,DC1241B-BA,DC1250A-AA,DC1250A-AD,DC1250A-BA |
| Export Control | no | no |
| Features | Internal Dither, Data Output Randomizer, Clock Duty Cycle Stabilizer | Internal Dither, Data Output Randomizer, Clock Duty Cycle Stabilizer |
| I/O | Parallel CMOS, Parallel LVDS | Parallel CMOS, Parallel LVDS |
| Input Drive | Differential, Single-Ended | Differential, Single-Ended |
| Input Span | 424mVpp | 424mVpp |
| Internal Reference | yes | yes |
| Latency | 7 | 7 |
| Operating Temperature Range, °C | 0 to 70 | -40 to 85 |
| Power, mW | 1650 | 1650 |
| SFDR, dB | 86 | 86 |
| SINAD, dB | 72 | 72 |
| SNR, dB | 75 | 75 |
| Simultaneous | no | no |
| Speed, ksps | 130000 | 130000 |
| Supply Voltage Range | 3.3V | 3.3V |
生态计划
| LTM9001CV-AD#PBF | LTM9001IV-AD#PBF | |
|---|---|---|
| RoHS | Compliant | Compliant |
其他选择
文章
- Complete IF Receiver Has 16-Bit, 130Msps ADC, Fixed-Gain Amplifier and Antialias Filter in 11.25mm × 11.25mm uModule Package &mdash LT JournalPDF, 600 Kb, 档案已发布: Mar 19, 2008从文件中提取
模型线
系列: LTM9001-AD (2)
制造商分类
- Data Conversion > Analog-to-Digital Converters (ADC) > High Speed ADCs (Fs >=10Msps)
- Data Conversion > Signal Chain µModule Receivers