Datasheet Microchip ATMEGA328PB-AN — 数据表

ATmega328PB
AVRВ® Microcontroller with Core Independent Peripherals
and PicoPowerВ® Technology
Introduction
В® В® The picoPower ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves
throughputs close to 1 MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed. Features
High Performance, Low-Power AVRВ® 8-bit Microcontroller Family Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-Chip 2-Cycle Multiplier High Endurance Nonvolatile Memory Segments
– 32 KB of In-System Self-Programmable Flash program memory
– 1 KB EEPROM
– 2 KB Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Programming Lock for Software Security
Peripheral Features
– Peripheral Touch Controller (PTC) Capacitive Touch Buttons, Sliders, and Wheels 24 Self-Cap Channels and 144 Mutual Cap Channels
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode …

This is a summary document. A
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our Web site at www.microchip.com ATmega328PB
ATmega328PB Summary Datasheet
Introduction
В® The picoPower ATmega328PB is a low-power CMOS 8-bit microcontroller based on the AVRВ® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega328PB achieves
throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed. Features
High Performance, Low Power AVRВ® 8-Bit Microcontroller Family Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-Chip 2-Cycle Multiplier High Endurance Non-Volatile Memory Segments
– 32KBytes of In-System Self-Programmable Flash program memory
– 1KBytes EEPROM
– 2KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C
– Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation
– Programming Lock for Software Security Peripheral Features …