Datasheet Texas Instruments 66AK2H14DAAWA24 — 数据表
| 制造商 | Texas Instruments |
| 系列 | 66AK2H14 |
| 零件号 | 66AK2H14DAAWA24 |
多核DSP + ARM KeyStone II片上系统（SoC）1517-FCBGA -40至100
数据表
66AK2Hxx Multicore DSP+ARMВ® KeyStone II System-on-Chip (SoC) datasheet
PDF, 2.4 Mb, 修订版: F, 档案已发布: Jun 2, 2017
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 1517 | 1517 | 1517 |
| Package Type | AAW | AAW | AAW |
| Package QTY | 21 | 21 | 21 |
| Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
| Device Marking | A1.2GHZ/1.4GHZ | 66AK2H14AAW | @2012 TI |
| Width (mm) | 40 | 40 | 40 |
| Length (mm) | 40 | 40 | 40 |
| Thickness (mm) | 3.07 | 3.07 | 3.07 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| ARM CPU | 4 ARM Cortex-A15 |
| ARM MHz | 1200,1400 Max. |
| Applications | Automation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space |
| DRAM | DDR3,DDR3L |
| DSP | 8 C66x |
| DSP MHz | 1200 Max. |
| EMAC | 10G Ethernet |
| Hardware Accelerators | Packet Accelerator,Security Accelerator |
| I2C | 3 |
| On-Chip L2 Cache | 4096 KB (ARM Cluster),1024 KB (per C66x DSP core) |
| Operating Systems | Integrity,Linux,SYS/BIOS,VxWorks |
| Operating Temperature Range | -40 to 100,0 to 85 C |
| Other On-Chip Memory | 6144 KB |
| PCI/PCIe | 2 PCIe Gen2 |
| Rating | Catalog |
| SPI | 3 |
| UART | 2 SCI |
| USB | 1 |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU200-U
XDS200 USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: EVMK2H
66AK2H Evaluation Modules
Lifecycle Status: Active (Recommended for new designs)
应用须知
- PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)PDF, 57 Kb, 修订版: A, 档案已发布: May 19, 2017
- Keystone II DDR3 InitializationPDF, 73 Kb, 档案已发布: Jan 26, 2015
This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller. - Throughput Performance Guide for KeyStone II Devices (Rev. B)PDF, 866 Kb, 修订版: B, 档案已发布: Dec 22, 2015
This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access. - Keystone II DDR3 Debug GuidePDF, 143 Kb, 档案已发布: Oct 16, 2015
This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device. - Power Management of KS2 Device (Rev. C)PDF, 61 Kb, 修订版: C, 档案已发布: Jul 15, 2016
This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices. - Hardware Design Guide for KeyStone II DevicesPDF, 1.8 Mb, 档案已发布: Mar 24, 2014
- SERDES Link Commissioning on KeyStone I and II DevicesPDF, 138 Kb, 档案已发布: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices. - PCIe Use Cases for KeyStone DevicesPDF, 320 Kb, 档案已发布: Dec 13, 2011
- The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)PDF, 20 Kb, 修订版: A, 档案已发布: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM - Clocking Design Guide for KeyStone DevicesPDF, 1.5 Mb, 档案已发布: Nov 9, 2010
- Optimizing Loops on the C66x DSPPDF, 585 Kb, 档案已发布: Nov 9, 2010
- DDR3 Design Requirements for KeyStone Devices (Rev. B)PDF, 582 Kb, 修订版: B, 档案已发布: Jun 5, 2014
- Multicore Programming Guide (Rev. B)PDF, 1.8 Mb, 修订版: B, 档案已发布: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore - Processor SDK RTOS Audio Benchmark Starter KitPDF, 530 Kb, 档案已发布: Apr 12, 2017
The TI TMS320C6000в„ў Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications that are commonly used in audio processing application. This application notes describes Audio Benchmark Starterkit software that is intended to provide an easy and quick way to benchmark key audio functions on C66x and C674x DSP device - TI DSP BenchmarkingPDF, 62 Kb, 档案已发布: Jan 13, 2016
This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
模型线
系列: 66AK2H14 (6)
- 66AK2H14BAAW24 66AK2H14BAAWA24 66AK2H14BXAAW24 66AK2H14DAAW24 66AK2H14DAAWA24 66AK2H14DXAAWA24
制造商分类
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP + ARM Processors > 66AK2x