Datasheet Texas Instruments 74SSTUB32865AZJBR — 数据表

74SSTUB32865A
www.ti.com SLAS562 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST
FEATURES 1 Member of the Texas Instruments Widebus+в„ў
Family Pinout Optimizes DDR2 RDIMM PCB Layout 1-to-2 Outputs Supports Stacked DDR2
RDIMMs High driver strength for heavily loaded DIMMs Chip-Select Inputs Gate the Data Outputs from
Changing State and Minimizes System Power
Consumption Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
2 Supports SSTL_18 Data Inputs
Differential Clock (CK and CK) Inputs
Supports LVCMOS Switching Levels on the
Chip-Select Gate-Enable and RESET Inputs
Checks Parity on DIMM-Independent Data
Inputs
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low, Except PTYERR
Supports industrial temperature range (-40В°C
to 85В°C) DESCRIPTION
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM
is required to drive up to stacked 18 SDRAM loads or two devices per DIMM are required to drive up to 36
stacked SDRAM loads.
All inputs are SSTL_18, except the chip-select gate-enable (CSGateEN) and reset (RESET) inputs, which are …