Datasheet Texas Instruments 74SSTUB32865ZJBR — 数据表
| 制造商 | Texas Instruments |
| 系列 | 74SSTUB32865 |
| 零件号 | 74SSTUB32865ZJBR |
具有地址奇偶测试160-NFBGA的28位至56位寄存器缓冲器-40至85
数据表
28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST datasheet
PDF, 766 Kb, 档案已发布: Nov 19, 2007
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 160 |
| Package Type | ZJB |
| Industry STD Term | NFBGA |
| JEDEC Code | R-PBGA-N |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | SB865 |
| Width (mm) | 9 |
| Length (mm) | 13 |
| Thickness (mm) | .77 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | N/A ps |
| Function | DDR2 Register |
| Number of Outputs | 56 |
| Operating Frequency Range(Max) | 410 MHz |
| Operating Temperature Range | -40 to 85 C |
| Output Drive | 8 mA |
| Package Group | NFBGA |
| Package Size: mm2:W x L | 160NFBGA: 117 mm2: 9 x 13(NFBGA) PKG |
| Rating | Catalog |
| VCC | 1.8 V |
| t(phase error) | N/A ps |
| tsk(o) | N/A ps |
生态计划
| RoHS | Compliant |
应用须知
- DDR2 Memory Interface Clocks and Registers - OverviewPDF, 308 Kb, 档案已发布: Mar 25, 2009
This application report gives an overview of the existing JEDEC DDR2 Register and PLL Buffer specifications and compliant TI devices.
模型线
系列: 74SSTUB32865 (1)
- 74SSTUB32865ZJBR
制造商分类
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers