Datasheet Analog Devices AD9635BCPZRL7-125 — 数据表

FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V supply operation
Low power: 115 mW per channel at 125 MSPS with scalable
power options
SNR = 71 dBFS (to Nyquist)
SFDR = 93 dBc at 70 MHz
DNL = −0.1 LSB to +0.2 LSB (typical); INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced
range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode AVDD APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems …