Datasheet Analog Devices AD9634BCPZRL7-250 — 数据表

FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 87 dBc at 185 MHz AIN and 250 MSPS
−150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 360 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy-saving power-down modes VIN+ PIPELINE
12-BIT
ADC VIN–
VCM DRVDD AGND AVDD 12 D0±/D1±
PARALLEL
DDR LVDS
AND
DRIVERS AD9634
REFERENCE . D10±/D11± DCO± …