Datasheet Analog Devices AD9628BCPZ-105 — 数据表

12-Bit, 125/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter
AD9628 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation
1.8 V CMOS or LVDS outputs
SNR = 71.2 dBFS @ 70 MHz
SFDR = 93 dBc @ 70 MHz
Low power: 101 mW/channel @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.25 LSB
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment AVDD PROGRAMMING DATA VIN+A VREF
SENSE
VCM AD9628 REF …