Datasheet Analog Devices AD9613BCPZRL7-170 — 数据表

FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS
SFDR = 86 dBc at 185 MHz fIN and 250 MSPS
−149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and
250 MSPS
Total power consumption: 770 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
Energy-saving power-down modes AVDD VIN+A PIPELINE
12-BIT
ADC VIN–A
VCM 12 AD9613 VIN+B PIPELINE
12-BIT
ADC VIN–B DRVDD AGND 12 D0± PARALLEL
DDR LVDS …