Datasheet Microchip ATUC64D3 — 数据表

Feature Summary 32-bit load/store RISC architecture
Up to 15 general-purpose 32-bit registers
32-bit Stack Pointer, Program Counter, and Link Register reside in register file
Fully orthogonal instruction set
Pipelined architecture allows one instruction per clock cycle for most instructions
Byte, half-word, word and double word memory access
Fast interrupts and multiple interrupt priority levels
Optional branch prediction for minimum delay branches
Privileged and unprivileged modes enabling efficient and secure Operating Systems
Innovative instruction set together with variable instruction length ensuring industry
leading code density
Optional DSP extention with saturated arithmetic, and a wide variety of multiply
instructions
Optional extensions for Java, SIMD, Read-Modify-Write to memory, and Coprocessors
Architectural support for efficient On-Chip Debug solutions
Optional MPU or MMU allows for advanced operating systems
FlashVaultв„ў support through Secure State for executing trusted code alongside
nontrusted code on the same CPU AVR32
Architecture
Document 32000D–04/2011 1. Introduction
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive
embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow for a variety of
microarchitectures, enabling the AVR32 to be implemented as low-, mid-or high-performance …

Features High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instructions
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performance Up to 61 DMIPS Running at 48MHz from Flash (1 Flash Wait State) Up to 34 DMIPS Running at 24MHz from Flash (0 Flash Wait State)
Multi-Hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 7 Peripheral DMA Channels Improve Speed for Peripheral Communication
Internal High-Speed Flash
– 128Kbytes, and 64Kbytes Versions
– Single-Cycle Access up to 24MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 16Kbytes
Interrupt Controller (INTC)
– Autovectored Low Latency Interrupt Service with Programmable Priority
External Interrupt Controller (EIC)
System Functions
– Power and Clock Manager
– SleepWalking™ Power Saving Control
– Internal System RC Oscillator (RCSYS)
– 32 KHz Oscillator …

Features High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instructions
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performance Up to 61 DMIPS Running at 48MHz from Flash (1 Flash Wait State) Up to 34 DMIPS Running at 24MHz from Flash (0 Flash Wait State)
Multi-Hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 7 Peripheral DMA Channels Improve Speed for Peripheral Communication
Internal High-Speed Flash
– 128Kbytes, and 64Kbytes Versions
– Single-Cycle Access up to 24MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 16Kbytes
Interrupt Controller (INTC)
– Autovectored Low Latency Interrupt Service with Programmable Priority
External Interrupt Controller (EIC)
System Functions
– Power and Clock Manager
– SleepWalking™ Power Saving Control
– Internal System RC Oscillator (RCSYS)
– 32 KHz Oscillator …

Feature Summary Small area, high clock frequency.
32-bit load/store AVR32A RISC architecture.
15 general-purpose 32-bit registers.
32-bit Stack Pointer, Program Counter and Link Register reside in register file.
Fully orthogonal instruction set.
Pipelined architecture allows one instruction per clock cycle for most instructions.
Byte, half-word, word and double word memory access.
Fast interrupts and multiple interrupt priority levels.
Privileged and unprivileged modes enabling efficient and secure Operating Systems.
Optional MPU allows for operating systems with memory protection.
Innovative instruction set together with variable instruction length ensuring industry
leading code density.
DSP extention with saturating arithmetic, and a wide variety of multiply instructions.
Memory Read-Modify-Write instructions.
Optional advanced On-Chip Debug system.
FlashVaultв„ў support through Secure state for executing trusted code alongside
nontrusted code on the same CPU.
Optional floating-point hardware. AVR32UC
Technical
Reference
Manual 32002F–03/2010 AVR32
1. Introduction
AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive …