Datasheet Microchip PIC32MX675F512L — 数据表

PIC32MX5XX/6XX/7XX
32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)
with Graphics Interface, USB, CAN, and Ethernet
Operating Conditions Timers/Output Compare/Input Capture 2.3V to 3.6V, -40ВєC to +105ВєC, DC to 80 MHz В® Core: 80 MHz/105 DMIPS MIPS32 M4K Five General Purpose Timers:
-Five 16-bit and up to two 32-bit Timers/Counters Five Output Compare (OC) modules Five Input Capture (IC) modules Real-Time Clock and Calendar (RTCC) module В® MIPS16eВ® mode for up to 40% smaller code size Code-efficient (C and Assembly) architecture Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Communication Interfaces Clock Management USB 2.0-compliant Full-Speed OTG controller 10/100 Mbps Ethernet MAC with MII and RMII interface CAN module:
-2.0B Active with DeviceNetв„ў addressing support Six UART modules (20 Mbps):
-Supports LIN 2.1 protocols and IrDAВ® support Up to four 4-wire SPI modules (25 Mbps) Up to five I2C modules (up to 1 Mbaud) with SMBus
support Parallel Master Port (PMP) 0.9% internal oscillator (on some variants)
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer
Fast wake-up and start-up Power Management Low-power management modes (Sleep and Idle)
Integrated Power-on Reset, Brown-out Reset
0.5 mA/MHz dynamic current (typical)
41 ВµA IPD current (typical) Direct Memory Access (DMA) Up to eight channels of hardware DMA with automatic
data size detection 32-bit Programmable Cyclic Redundancy Check (CRC) Six additional channels dedicated to USB, Ethernet and
CAN modules Graphics Features External graphics interface with up to 34 Parallel Master
Port (PMP) pins:
-Interface to external graphics controller
-Capable of driving LCD directly with DMA and
internal or external memory Input/Output 15 mA or 10 mA source/sink for standard VOH/VOL and
up to 22 mA for non-standard VOH1 5V-tolerant pins Selectable open drain and pull-ups External interrupts Analog Features ADC Module:
-10-bit 1 Msps rate with one Sample and Hold (S&H) …