Datasheet Microchip ATMEGA324PB-ANR — 数据表

ATmega324PB
AVR Microcontroller with Core Independent Peripherals
and PicoPower technology
Introduction
В® The picoPower ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVRВ® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves
throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed. Feature
High Performance, Low Power AVRВ® 8-Bit Microcontroller Family Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-Chip 2-cycle Multiplier High Endurance Non-Volatile Memory Segments
– 32KBytes of In-System Self-Programmable Flash Program Memory
– 1KBytes EEPROM
– 2KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 Years at 85°C
– Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation
– Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-Scan Capabilities According to the JTAG Standard …

This is a summary document. A
complete document is available on
our Web site at www.microchip.com ATmega324PB Summary
AVR Microcontroller with Core Independent Peripherals
and PicoPower technology
Introduction
В® The picoPower ATmega324PB is a low-power CMOS 8-bit microcontroller based on the AVRВ® enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PB achieves
throughputs close to 1MIPS per MHz. This empowers system designers to optimize the device for power
consumption versus processing speed. Feature
High Performance, Low Power AVRВ® 8-Bit Microcontroller Family Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-Chip 2-cycle Multiplier High Endurance Non-Volatile Memory Segments
– 32KBytes of In-System Self-Programmable Flash Program Memory
– 1KBytes EEPROM
– 2KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 Years at 85°C
– Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation …