Datasheet Microchip PIC18LF26K40-I/SP — 数据表

PIC18(L)F26/45/46K40
28/40/44-Pin, Low-Power, High-Performance
Microcontrollers with XLP Technology
Description
These PIC18(L)F26/45/46K40 microcontrollers feature Analog, Core Independent Peripherals and
Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of
general purpose and low-power applications. These 28/40/44 -pin devices are equipped with a 10-bit
ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced
touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They
also offer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG),
Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross
Detect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system
cost. Core Features
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• C Compiler Optimized RISC Architecture …

PIC18(L)F26/45/46K40
28/40/44-Pin, Low-Power, High-Performance
Microcontrollers with XLP Technology
Description
These PIC18(L)F26/45/46K40 microcontrollers feature Analog, Core Independent Peripherals and
Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of
general purpose and low-power applications. These 28/40/44 -pin devices are equipped with a 10-bit
ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced
touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They
also offer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG),
Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross
Detect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system
cost. Core Features C Compiler Optimized RISC Architecture
Operating Speed:
– DC – 64 MHz clock input over the full VDD range
– 62.5 ns minimum instruction cycle
Programmable 2-Level Interrupt Priority
31-Level Deep Hardware Stack
Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Four 16-Bit Timers (TMR0/1/3/5)
Low-Current Power-on Reset (POR)
Power-up Timer (PWRT)
Brown-out Reset (BOR) …