Datasheet Microchip ATSAMC21J16A-ANT — 数据表

SAM C20/C21
32-bit ARM Cortex-M0+ with 5V Support, CAN-FD, PTC,
and Advanced Analog
Features
Operating Conditions 2.7V – 5.5V, -40°C to +105°C, DC to 48 MHz
Core ARMВ® CortexВ®-M0+ CPU running at up to 48 MHz
– Single-cycle hardware multiplier
– Micro Trace Buffer
– Memory Protection Unit (MPU)
Memories 32/64/128/256 KB in-system self-programmable Flash 1/2/4/8 KB independent self-programmable Flash for EEPROM emulation 4/8/16/32 KB SRAM Main Memory
System Power-on Reset (POR) and Brown-out Detection (BOD) Internal and external clock options with 48 MHz to 96 MHz Fractional Digital Phase Locked Loop
(FDPLL96M) External Interrupt Controller (EIC) (Interrupt pin debouncing is only available in SAM C21N) 16 external interrupts
– Hardware debouncing (only on the 100Pin TQFP) One non-maskable interrupt Two-pin Serial Wire Debug (SWD) programming, test, and debugging interface
Low-Power Idle and Standby Sleep modes SleepWalking peripherals Peripherals Hardware Divide and Square Root Accelerator (DIVAS) 12-channel Direct Memory Access Controller (DMAC) 12-channel Event System Up to eight 16-bit Timer/Counters (TC), configurable as either (see Note):
Note:  Maximum and minimum capture is only available in SAM C21N devices.
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– One 16-bit TC with compare/capture channels
One 8-bit TC with compare/capture channels
One 32-bit TC with compare/capture channels, by using two TCs В© 2017 Microchip Technology Inc. Datasheet DS60001479B-page 1 SAM C20/C21 I/O Two 24-bit Timer/Counters and one 16-bit Timer/Counter for Control (TCC), with extended functions:
– Up to four compare channels with optional complementary output
– Generation of synchronized pulse width modulation (PWM) pattern across port pins
– Deterministic fault protection, fast decay and configurable dead-time between complementary …