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LTC4302 LTC4302-1

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• 下载
  Addressable IВІC Bus Buffer Provides Capacitance Buffering, Live Insertion and Nested Addressing in 2-Wire Bus Systems &mdash DN329
  PDF, 129 Kb, 档案已发布: Jan 2, 2004
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  advertisement Addressable I2C Bus Buffer Provides Capacitance Buffering,
  Live Insertion and Nested Addressing in 2-Wire Bus Systems
  Design Note 329
  John Ziegler
  Introduction
  In an effort to improve the reliability of large data processing, data storage and communications systems, their
  subsystems include a growing number of active circuits
  to monitor parameters such as temperature, fan speed
  and system voltages. Individual subsystem monitors
  often communicate with the host system through 2-wire
  serial busses, such as SMBus or I2CTM, to a dedicated
  microcontroller.
  As monitoring functions increase in complexity and number, several practical problems arise. First, data bus rise
  time specifications become difficult to meet. Second,
  many uninterruptible systems cannot tolerate cycling
  power whenever a new I/O card is installed. Finally, a
  device’s address is often dictated by the function that it
  performs. If an existing system already contains a temperature sensor, for example, then inserting a new I/O
  card with a temperature sensor risks having two devices
  with the same address. The new LTCВ®4302-1/LTC4302-2,
  addressable 2-wire bus buffers provide solutions to all of
  these problems. Live Insertion and Removal and
  Capacitance Buffering Application …

文章

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  Redundant 2-Wire Bus for High Reliability Systems &mdash LT Journal
  PDF, 329 Kb, 档案已发布: Mar 25, 2005
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  DESIGN IDEAS Redundant 2-Wire Bus for
  High Reliability Systems
  Introduction
  The effort to achieve high reliability
  in data processing, data storage and
  communication systems has necessitated the use of circuitry to monitor
  parameters such as temperature, fan
  speed, and system voltages. These
  circuits often communicate through
  2-wire serial buses, such as SMBus
  or I2C. Redundant subsystems are
  important in high reliability systems,
  and the 2-wire bus subsystem is
  no exception. High reliability 2-wire
  bus systems incorporate two master
  controllers in a redundant configuration, to maintain system operation if
  one master fails or is removed. In a
  redundant configuration, each master is connected to its own 2-wire bus,
  while all of the slaves are connected to
  a single downstream redundant bus.
  Either master can take control of the
  redundant bus at any time.
  Figure 1 shows a circuit using …

• 下载
  Addressable Bus Buffer Provides Capacitance Buffering, Live Insertion and Nested Addressing in 2-WireBus Systems &mdash LT Journal
  PDF, 216 Kb, 档案已发布: Sep 1, 2003
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  DESIGN FEATURES Addressable Bus Buffer Provides
  Capacitance Buffering, Live
  Insertion and Nested Addressing
  by John Ziegler
  in 2-WireBus Systems
  Introduction The reliability of data processing,
  data storage and communications
  systems depends in part on how
  well the system is monitored. To this
  end, input/output (I/O) cards contain circuitry to monitor parameters
  such as temperature, fan speed and
  system voltages. These circuits often
  communicate through 2-wire serial
  buses, such as SMBus or I2C.
  Several practical problems can
  occur in these systems, especially
  as they become large. First, data
  bus rise time specifications become
  difficult to meet, as the SDA (serial
  data) and SCL (serial clock) capacitances of each I/O card add directly
  to those of the backplane, while the
  pull-up impedance remains constant.
  Second, cycling power whenever a new …

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• Interface > I2C and SMBus Bus Buffers and Accelerators