Datasheet Intersil HCS161MS — 数据表

DATASHEET
HCS161MS FN2469
Rev 2.00
September 1995 Radiation Hardened Synchronous Counter Features Pinouts 3 Micron Radiation Hardened SOS CMOS 16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16
TOP VIEW Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ) MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE GND 8 Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse Cosmic Ray Upset Immunity 2 x
(Typ) 10-9 Error/Bit Day Latch-Up Free Under Any Conditions Military Temperature Range: -55oC to +125oC 9 SPEN Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels
-VIL = 0.3 VCC Max
-VIH = 0.7 VCC Min 16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16
TOP VIEW Input Current Levels Ii п‚Ј 5пЃ­A at VOL, VOH Description
The Intersil HCS161MS is a Radiation Hardened 4-Input
Binary; synchronous counter featuring asynchronous reset
and look-ahead carry logic. The HCS161 has an active-low
master reset to zero, MR. A low level at the synchronous
parallel enable, SPE, disables counting and allows data at
the preset inputs (p0 -p3) to load the counter. The data is
latched to the outputs on the positive edge of the clock input,
CP. The HCS161MS has two count output, IC. The terminal
count output indicates a maximum count for one clock pulse …