DATASHEET
CD4099BMS FN3333
Rev 0.00
December 1992 CMOS 8-Bit Addressable Latch Features Pinout High Voltage Type (20V Rating) CD4099BMS
TOP VIEW Serial Data Input Active Parallel Output Storage Register Capability Q7 1 16 VDD RESET Master Clear Can Function as Demultiplexer 2 15 Q6 DATA 3 14 Q5 WRITE DISABLE 4 13 Q4 100% Tested for Quiescent Current at 20V A0 5 12 Q3 5V, 10V and 15V Parametric Ratings A1 6 11 Q2 Standardized Symmetrical Output Characteristics A2 7 10 Q1 VSS 8 9 Q0 Maximum Input Current of 1пЃA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Over Full Package/Temperature Range)
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
�B’ Series CMOS Devices” Functional Diagram WRITE DISABLE Applications DATA Multi-Line Decoders
A0 A/D Converters A1 Description A2 10 8
DECODER 12
8 LATCHES 7 13
14 CD4099BMS 8-bit addressable latch is a serial input, parallel
output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit
is addressed (by means of inputs A0, A1, A2) and when
WRITE DISABLE is at a low level. When WRITE DISABLE is
high, data entry is inhibited; however, all 8 outputs can be
continuously read independent of WRITE DISABLE and
address inputs. 9 3 11 5
6 4 15
2 RESET 1 Q0 …
