Datasheet Intersil CD4015BMS — 数据表

DATASHEET
CD4015BMS FN3295
Rev 0.00
December 1992 CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output Features Pinout High-Voltage Type (20V Rating) Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD -VSS = 10V CD4015BMS
TOP VIEW
16 VDD CLOCK B 1 Fully Static Operation Q4B 2 15 DATA B 8 Master-Slave Flip-Flops Plus Input and Output Buffering Q3A 3 14 RESET B 100% Tested For Quiescent Current at 20V Q2A 4 13 Q1B 5V, 10V and 15V Parametric Ratings Q1A 5 12 Q2B RESET A 6 11 Q3B DATA A 7 10 Q4A Standardized Symmetrical Output Characteristics Maximum Input Current of 1пЃ­A at 18V Over Full Package-Temperature Range; 100nA at 18V and 25oC 9 CLOCK A VSS 8 Noise Margin (Full Package-Temperature Range) =
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
�B’ Series CMOS Devices” Functional Diagram
VDD
16
DATA A Applications Serial-Input/Parallel-Output Data Queueing Serial to Parallel Data Conversion CLOCK A
RESET A DATA B
CLOCK B CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial
DATA input. “Q” outputs are available from each of the four
stages on both registers. All register stages are D type, master-slave flip-flops. The logic level present at the DATA input
is transferred into the first register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line. …