Datasheet Microchip PL502-37OC-R — 数据表

PL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise ICs FEATURES 1 XIN 2 XOUT 3 SEL3^ 4 SEL2^ 5 OE 6 VCON 7 GND 8 9 SEL[3:0] XOUT VDD
CLKT
GND
GND VDD / GND* SEL0^ / VDD* SEL1^ 12 11 10 9 13 8 GND SEL3^ 14 7 CLKC SEL2^ 15 6 VDD OE 16 5 CLKT 2 3 4 GND VCON 1 GND PL502-3x QFN-16L OE XIN CLKC XOUT PL502-38
PLL
(Phase
Locked
Loop) GND Internal pull-up
On 3x3 package, PL502-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL502 -37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details. Part # Oscillator
Amplifier
w/
integrated
varicaps SEL1^ OUTPUT ENABLE LOGICAL LEVELS BLOCK DIAGRAM VCON SEL0^ TSSOP-16L
^:
*: DESCRIPTION
The PL502-35 (LVPECL with inverted OE), PL502-37
(LVCMOS), PL502-38 (LVPECL), and PL502-39
(LVDS) are high performance and low phase noise
VCXO IC chips. They provide phase noise performance as low as –125dBc at 10kHz offset (at …