Datasheet Texas Instruments THS4271D — 数据表
| 制造商 | Texas Instruments |
| 系列 | THS4271 |
| 零件号 | THS4271D |
超快速超低失真高速放大器8-SOIC -40至85
数据表
Low Noise, High Slew Rate, Unity Gain Stable Voltage Feedback Amplifier datasheet
PDF, 1.7 Mb, 修订版: F, 档案已发布: Oct 16, 2009
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 8 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 75 |
| Carrier | TUBE |
| Device Marking | 4271 |
| Width (mm) | 3.91 |
| Length (mm) | 4.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | 下载 |
参数化
| 2nd Harmonic | 65 dBc |
| 3rd Harmonic | 80 dBc |
| @ MHz | 30 |
| Acl, min spec gain | 1 V/V |
| Additional Features | N/A |
| Architecture | Bipolar,Voltage FB |
| BW @ Acl | 1400 MHz |
| CMRR(Min) | 67 dB |
| CMRR(Typ) | 72 dB |
| GBW(Typ) | 1400 MHz |
| Input Bias Current(Max) | 15000000 pA |
| Iq per channel(Max) | 24 mA |
| Iq per channel(Typ) | 22 mA |
| Number of Channels | 1 |
| Offset Drift(Typ) | 10 uV/C |
| Operating Temperature Range | -40 to 85 C |
| Output Current(Typ) | 160 mA |
| Package Group | SOIC |
| Package Size: mm2:W x L | 8SOIC: 29 mm2: 6 x 4.9(SOIC) PKG |
| Rail-to-Rail | No |
| Rating | Catalog |
| Slew Rate(Typ) | 1000 V/us |
| Total Supply Voltage(Max) | 10 +5V=5, +/-5V=10 |
| Total Supply Voltage(Min) | 5 +5V=5, +/-5V=10 |
| Vn at 1kHz(Typ) | 3 nV/rtHz |
| Vn at Flatband(Typ) | 3 nV/rtHz |
| Vos (Offset Voltage @ 25C)(Max) | 10 mV |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: THS4271EVM
THS4271 Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: THS4271EVM-UG
THS4271 Evaluation Module with Unity Gain
Lifecycle Status: Active (Recommended for new designs)
应用须知
- Wideband Complementary Current Output DAC Single-Ended InterfacePDF, 597 Kb, 档案已发布: Jun 21, 2005
High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA - Noise Analysis for High Speed Op Amps (Rev. A)PDF, 256 Kb, 修订版: A, 档案已发布: Jan 17, 2005
As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu
模型线
系列: THS4271 (11)
制造商分类
- Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > High-Speed Op Amps (>=50MHz)