Datasheet Texas Instruments ADS5500IPAP — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS5500 |
| 零件号 | ADS5500IPAP |
14位125MSPS模数转换器（ADC）64-HTQFP -40至85
数据表
14-Bit, 125MSPS Analog-to-Digital Converter datasheet
PDF, 1.8 Mb, 修订版: F, 档案已发布: Feb 8, 2007
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 64 |
| Package Type | PAP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 160 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | ADS5500I |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 1 |
| Analog Input BW | 750 MHz |
| Architecture | Pipeline |
| DNL(Max) | 0.75 +/-LSB |
| DNL(Typ) | 0.75 +/-LSB |
| ENOB | 11.3 Bits |
| INL(Max) | 2.5 +/-LSB |
| INL(Typ) | 2.5 +/-LSB |
| Input Buffer | No |
| Input Range | 2.3 Vp-p |
| Interface | Parallel CMOS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 64HTQFP: 144 mm2: 12 x 12(HTQFP) PKG |
| Power Consumption(Typ) | 780 mW |
| Rating | Catalog |
| Reference Mode | Int |
| Resolution | 14 Bits |
| SFDR | 83 dB |
| SINAD | 71.6 dB |
| SNR | 72.3 dB |
| Sample Rate(Max) | 125 MSPS |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: DEM-OPA-ADS-SO-1A
DEM-OPA-ADS-SO-1A
Lifecycle Status: Preview (Device has been announced but is not in production. Samples may or may not be available) - Evaluation Modules & Boards: THS4509EVM
THS4509EVM Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
应用须知
- Implementing a CDC7005 Low Jitter Clock Solution for HIgh Speed High IF ADC DevPDF, 627 Kb, 档案已发布: Jun 25, 2004
Texas Instruments has introduced a family of devices suited to meet the demand for high-speed, high-IF sampling ADC devices like the ADS5500 ADC, capable of sampling at 125 MSPS. To realize the full potential of these high performance devices, it is imperative to provide an extremely low phase noise clock source. The CDC7005 clock distribution chip offers a real-world clocking solution to meet the - 14-Bit, 125-MSPS ADS5500 EvaluationPDF, 738 Kb, 档案已发布: Jan 18, 2005
- Clocking High-Speed Data ConvertersPDF, 310 Kb, 档案已发布: Jan 18, 2005
- Low-power, high-intercept interface to the ADS5424, 105-MSPS converterPDF, 478 Kb, 档案已发布: Oct 10, 2005
- ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC DriversPDF, 273 Kb, 档案已发布: Apr 22, 2004
Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation - Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, 档案已发布: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
- Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
模型线
系列: ADS5500 (2)
- ADS5500IPAP ADS5500IPAPR
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)