Datasheet Analog Devices ADSP-BF701 — 数据表

Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
FEATURES MEMORY Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm), 
RoHS compliant
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION
AEC-Q100 qualified for automotive applications 136 kB L1 SRAM with multi-parity-bit protection 
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz) …

Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
FEATURES MEMORY Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm), 
RoHS compliant
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION 136 kB L1 SRAM with multi-parity-bit protection 
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz)
Security and one-time-programmable memory …