Datasheet Analog Devices ADAU1446YSTZ-3A-RL — 数据表

SigmaDSP Digital Audio Processor
with Flexible Audio Routing Matrix
ADAU1442/ADAU1445/ADAU1446 Data Sheet
FEATURES I2C and SPI control interfaces
Standalone operation
Self-boot from serial EEPROM
4-channel, 10-bit auxiliary control ADC
Multipurpose pins for digital controls and outputs
Easy implementation of available third-party algorithms
On-chip regulator for generating 1.8 V from 3.3 V supply
100-lead TQFP and LQFP packages
Temperature range: −40°C to +105°C Fully programmable audio digital signal processor (DSP) for
enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz
4k parameter RAM, 8k data RAM
Flexible audio routing matrix (FARM)
24-channel digital input and output
Up to 8 stereo asynchronous sample rate converters
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)
Stereo S/PDIF input and output
Supports serial and TDM I/O, up to fS = 192 kHz …

Silicon Anomaly SigmaDSP Digital Audio Processor with
Flexible Audio Routing Matrix
ADAU1442/ADAU1445/ADAU1446 This anomaly list describes the known bugs, anomalies, and workarounds for the ADAU1442/ADAU1445/ADAU1446.
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improving silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here. ADAU1442/ADAU1445/ADAU1446 FUNCTIONALITY ISSUES
Silicon Status
Release Anomaly Sheet
Rev. 0 No. of Reported Anomalies
1 FUNCTIONALITY ISSUES
Table 1. S/PDIF Transmitter Validity Bit Setting [er001]
Background Issue Workaround Related Issues The S/PDIF transmitter outputs two channels of audio data directly from the DSP core at the core rate. It does not
preserve or output any additional nonaudio information encoded in the S/PDIF input stream, such as the validity
bit, user data, and channel status. The encoded nonaudio data bits in the S/PDIF output stream are hardwired
internally to logic low values, except for the validity bit, which is set as logic high.
In the S/PDIF specification, a high validity bit indicates invalid data. For this reason, if the output from the
ADAU1442/ADAU1445/ADAU1446 SPDIFO pin is connected directly to an S/PDIF receiver IC, the receiver may
ignore or discard the transmitted audio data because the high validity bit indicates an error. Alternatively, some
S/PDIF receivers (including the ADAU1442/ADAU1445/ADAU1446 SPDIFI pin) may ignore the validity bit and
pass the data through.
This issue cannot be avoided because the validity bit value is internally hardcoded. If an S/PDIF output is
required in the system, audio data can instead be routed to the ADAU1442/ADAU1445/ADAU1446 serial ports
and then to an I2S-to-S/PDIF transceiver IC. …