Datasheet Analog Devices LTC6950IUHH#PBF — 数据表

LTC6950
1.4GHz Low Phase Noise,
Low Jitter PLL with Clock
Distribution
Description Features Low Phase Noise and Jitter
n Additive Jitter: 18fs
RMS (12kHz to 20MHz)
n Additive Jitter: 85fs
RMS (10Hz to Nyquist)
n EZSync™ Multichip Clock Edge Synchronizatio Full PLL Core with Lock Indicator
n –226dBc/Hz Normalized In-Band Phase Noise Floor
n –274dBc/Hz Normalized 1/f Phase Noise
n 1.4GHz Maximum VCO Input Frequency
n Four Independent, Low Noise 1.4GHz LVPECL Outputs
n One LVDS/CMOS Configurable Output
n Five Independently Programmable Dividers Covering
All Integers from 1 to 63
n Five Independently Programmable VCO Clock Cycle
Delays Covering All Integers from 0 to 63
n –40°C to 105°C Junction Temperature Range
n Applications Clocking High Speed, High Resolution ADCs,
DACs and Data Acquisition Systems
n Low Jitter Clock Generation and Distributio The LTC®6950 is a low phase noise integer-N frequency …