Datasheet Analog Devices HMC988LP3ETR — 数据表

HMC988LP3E
v04.1014 Clock Distribution -SMT PROGRAMMABLE CLOCK DIVIDER AND DELAY
DC -4 GHz
Typical Applications Features The HMC988LP3E is ideal for: DC -4 GHz • Basestation Digital Pre-Distortion Paths(DPD) -170 dBc/Hz floor @ 100 MHz output • High Performance Automated Test
Equipment(ATE) -164 dBc/Hz floor @ 2 GHz output
Integrated Jitter 35 fsRMS@ 100 MHz output
13 fsRMS(calculated) @ 2 GHz output • Backplane clock skew management • Phase Coherence of multiple clock paths Adjustable output phase with soft/hard reset sync • Clock Delay management to improve setup &
hold time margins Flexible Input Interface: Adjustable output delay in 60 steps of 20 ps • PCB signal flight time offset circuits LVPECL,LVDS,CML,CMOS Compatible • Track and hold circuits for ADC/DACs AC or DC Coupling
On -Chip Termination 50 Ω (100 Ω Differential)
Output Driver (LVPECL): Functional Diagram 800 mVpp LVPECL into 50 Ω Single-Ended (+3
dBm Fo)
Up to 8 addressable dividers per SPI bus
3.3 V operation or 5 V operation with Optional onchip regulator for best performance
3 x 3 QFN Leadless SMT Package General Description
The HMC988LP3E is a an ultra low noise clock
divider capable of dividing by 1/2/4/8/16/32. It is a
versatile device with additional functionality including
adjustable output phase, adjustable delay in 60 steps
of ~ 20 ps, a clock synchronization function, and a
clock invert option.
Housed in a compact 3x3 mm SMT QFN package, the
clock divider offers a high level of functionality. The
device works with 3.3 V supply or may be connected …