Datasheet Analog Devices ADCLK846BCPZ-REEL7 — 数据表

1.8 V, 6 LVDS/12 CMOS Outputs
Low Power Clock Fanout Buffer
ADCLK846 Data Sheet
FEATURES FUNCTIONAL BLOCK DIAGRAM Selectable LVDS/CMOS outputs
Up to 6 LVDS (1.2 GHz) or 12 CMOS (250 MHz) outputs 1 V/ns, unless otherwise noted.
Table 1.
Parameter
CLOCK INPUTS
Input Frequency
Input Sensitivity, Differential Symbol Min Typ 0 Input Voltage Offset
Input Sensitivity, Single-Ended
Input Resistance (Differential)
Input Capacitance
Input Bias Current (Each Pin)
LVDS CLOCK OUTPUTS
Output Frequency
Differential Output Voltage
Offset Voltage
Short-Circuit Current Unit 1200 MHz
mV p-p 150 Input Level
Input Common-Mode Voltage
Input Common-Mode Range Max VCM
VCMR VS/2 − 0.1 …