Datasheet Analog Devices AD9520-0 — 数据表

Data Sheet 12 LVPECL/24 CMOS Output Clock
Generator with Integrated 2.8 GHz VCO
AD9520-0
FUNCTIONAL BLOCK DIAGRAM APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10GFC,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures GENERAL DESCRIPTION
The AD9520-0 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz
to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
1 1 LF CP REF1 REFIN REFIN CLK REF2 STATUS
MONITOR
PLL OPTIONAL SWITCHOVER
AND MONITOR Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.53 GHz to 2.95 GHz
Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz …