Datasheet Microchip PIC16F18345T-E/6NVAO — 数据表

PIC16(L)F18325/18345
Full-Featured, Low Pin Count Microcontrollers with XLP
Description
PIC16(L)F18325/18345 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications.
The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP,
PWM and communications) to add flexibility to the application design. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture
• Only 48 Instructions
• Operating Speed:
-DC – 32 MHz clock input
-125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Up to Four 8-bit Timers
• Up to Three 16-bit Timers
• Low-Current Power-on Reset (POR)
• Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Extended Watchdog Timer (WDT) with Dedicated
On-Chip Oscillator for Reliable Operation
• Programmable Code Protection • IDLE mode: ability to put the CPU core to Sleep
while internal peripherals continue operating from …

PIC16F18325/18345
Full-Featured, Low Pin Count, High-Temperature Microcontrollers
Description
PIC16(L)F18325/18345 high-temperature microcontrollers feature Intelligent Analog, Core Independent Peripherals
(CIPs) and Communication Peripherals, combined with an extended temperature range for a variety of general purpose
applications. The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals
Configurable Logic Cell (CLC), Complementary Waveform Generator (CWG), Capture/Compare/PWM (CCP), PulseWidth Modulation (PWM), and communications to add flexibility to the application design. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture
• Only 48 Instructions
• Operating Speed: • IDLE mode: ability to put the CPU core to Sleep
from the system clock, while internal peripherals
continue operating
• DOZE mode: ability to run the CPU core slower
than the system clock used by the internal
peripherals
• SLEEP mode: lowest power consumption
• Peripheral Module Disable (PMD): peripheral
power disable hardware module to minimize
power consumption of unused peripherals -DC – 32 MHz clock input
-125 ns minimum instruction cycle
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• …