Datasheet Analog Devices ADSP-21065LKCAZ264 — 数据表

a DSP Microcomputer
ADSP-21065L
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation SUMMARY
High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I2S Support, for Eight Simultaneous Receive and Transmit Channels Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators KEY FEATURES …

SHARC DSP Microcomputer
ADSP-21065L-EP Enhanced Product
SUMMARY ENHANCED PRODUCT (EP) FEATURES High performance signal computer for communications,
audio, automotive, instrumentation, medical, military, and
industrial applications
Super Harvard Architecture Computer (SHARC) — four independent buses for dual data, instruction, and I/O fetch on a
single cycle
32-bit fixed-point arithmetic; 32-bit and 40-bit floatingpoint arithmetic
544K bits on-chip SRAM memory and integrated I/O
peripheral
I2S support, for eight simultaneous receive and transmit
channels Supports defense and aerospace applications (AQEC
standard)
Extended temperature range –55°C to +110°C
Controlled manufacturing baseline
One package assembly/test site
One wafer fabrication site
Enhanced product change notification
Qualification data available upon request CORE PROCESSOR DAG1
8 × 4 × 32 TWO INDEPENDENT
DUAL-PORTED BLOCKS PROCESSOR PORT
I/O PORT
ADDR …