Datasheet Texas Instruments OMAP3530DCBB72 — 数据表

制造商	Texas Instruments
系列	OMAP3530
零件号	OMAP3530DCBB72

数据表

价格

状态

打包

参数化

生态计划

设计套件和评估模块

• Evaluation Modules & Boards: TMDSEVM3530
  OMAP35x Evaluation Module (EVM)
  Lifecycle Status: Active (Recommended for new designs)
  
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应用须知

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  OMAP3530 Power Consumption Summary
  PDF, 19 Kb, 档案已发布: Jan 8, 2010
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at: http://wiki.davincidsp.com/index.php/OMAP3530_Power_Estimation_Spreadsheet.

  Power consumption on the OMAP3530 device is highly application-dependent therefore a sp

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  OMAP3530 Easy CUS Package PCB Escape Routing (Rev. A)
  PDF, 2.6 Mb, 修订版: A, 档案已发布: Mar 25, 2010
  The OMAP3530 CUS package is designed with a new technology called Via Channel™ array. This technology allows for easy routing of the device in two signal and two power layers using standard 20 mil diameter and 10 mil finished hole size via; it is cost and time effective. This application report shows how to easily route the entire package by first routing one quadrant only and then copying i
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  Ultrasound Scan Conversion on TI's C64x+ DSPs
  PDF, 656 Kb, 档案已发布: Apr 3, 2009
  One of the recent significant developments in ultrasound is the emergence of portable and handheld ultrasound machines and their rapid acceptance in the market place.Because of their power efficiency and high performance digital signal processor (DSP) based devices have been increasingly used as the main processing engine in these portable and hand carried units.

  This application report dis

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  OMAP35x Linux PSP Data Sheet
  PDF, 1.6 Mb, 档案已发布: Oct 16, 2009
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  OMAP3530/25/15/03 CBB CBC & CUS Reflow Profiles
  PDF, 27 Kb, 档案已发布: Nov 13, 2009
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at:

  http://wiki.davincidsp.com/index.php/OMAP3_CBB_CBC_CUS_Reflow_Profiles

  Reflow profiles are dependent on numerous factors including package type number of components bo

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  OMAP35x 0.65mm Pitch Layout Methods (Rev. B)
  PDF, 372 Kb, 修订版: B, 档案已发布: Jun 26, 2008
  It is easy to see from the unique look that the OMAP35x parts have a very unusual footprint. The OMAP35x ball grid array is designed with new technology called the Via Channel array which makes significant printed circuit board (PCB) cost savings possible. If the PCB is routed correctly this cost savings can be substantial. This application report explains how this is possible and shows several
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  Powering OMAP3 With TPS65023: Design-In Guide (Rev. B)
  PDF, 181 Kb, 修订版: B, 档案已发布: Mar 2, 2009
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  OMAP35x to AM35x Hardware Migration Guide
  PDF, 19 Kb, 档案已发布: May 24, 2010
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at:

  http://processors.wiki.ti.com/index.php/OMAP35x_to_AM35x_Hardware_Migration_Guide.

  This article describes hardware device considerations to migrate a design

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  OMAP35x to AM37x Hardware Migration Guide
  PDF, 37 Kb, 档案已发布: Jun 3, 2010
  This article has been contributed to the TI Developer Wiki. To see the most recently updated version or to contribute visit this topic at:

  http://processors.wiki.ti.com/index.php/OMAP35x_To_AM37x_Hardware_Migration_Guide.

  The OMAP35x to AM37x Hardware Migration Guide describes device consideratio

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  PCB Design Guidelines for 0.4mm Package-On-Package (PoP) Packages Part I (Rev. B)
  PDF, 6.7 Mb, 修订版: B, 档案已发布: Jun 13, 2009
  Ball grid array (BGA) packages having 0.4mm ball pitch require careful attention to printed circuit board (PCB) design parameters to successfully yield reliable and robust assemblies; the standard rules of thumb don't apply anymore. In fact the design guidelines for 0.4mm and 0.5mm differ primarily due to issues surrounding shorts or opens between balls under the processor.In addition to the de
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  PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages Part II (Rev. A)
  PDF, 2.4 Mb, 修订版: A, 档案已发布: Nov 1, 2013
  Once the bottom circuit board has been designed the assembly guidelines for package-on-package (PoP) versions of the OMAP35xx processor and the memory device must be considered.

  PoP packages have an enormous number of variables associated with assembly. The following factors have a major effect on the quality and reliability of final assembly: the circuit board design the solder paste char

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  PCB Assembly Guidelines for 0.5mm Package-on-Package Apps Processors Part II
  PDF, 1.2 Mb, 档案已发布: Jun 23, 2010
  Once the main printed circuit board (PCB) has been designed the assembly guidelines for the 0.5mm package-on-package (PoP) applications processor and companion memory device must be considered. PoP applications processors have an enormous number of variables associated with assembly. The following factors have a major effect on the quality and reliability of PCB assembly: PoP applications process
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  PCB Design Guidelines for 0.5mm Package-On-Package Apps Processors Part I
  PDF, 2.0 Mb, 档案已发布: Jun 23, 2010
  Ball grid array (BGA) packages having 0.5mm ball pitch require careful attention to printed circuit board (PCB) design parameters to successfully yield reliable and robust assemblies. PCBs with package-on-package (PoP) technology have additional assembly requirements and options that need to be considered when designing the PCB.

  Fine-pitch PCB design is a team effort and may require more than

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  Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms
  PDF, 969 Kb, 档案已发布: Sep 24, 2009
  This application report describes the device differences to be taken care for running the C64x+™ video codec software on different C64x+ based platforms. This document assumes that the codec software is developed for the C64x+ digital signal processor (DSP) core. As many TI platforms have a C64x+ DSP this document gives the details for running the standalone codec software on a C64x+ platfo
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  Introduction to TMS320C6000 DSP Optimization
  PDF, 535 Kb, 档案已发布: Oct 6, 2011
  The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then

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