Datasheet Texas Instruments ADS5463IPFP — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADS5463 |
| 零件号 | ADS5463IPFP |
12位，500MSPS模数转换器（ADC）80-HTQFP -40至85
数据表
12-Bit 500-/550-MSPS Analog-to-Digital Converters datasheet
PDF, 2.0 Mb, 修订版: E, 档案已发布: Jul 1, 2009
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 80 |
| Package Type | PFP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 96 |
| Carrier | JEDEC TRAY (5+1) |
| Device Marking | ADS5463I |
| Width (mm) | 12 |
| Length (mm) | 12 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| # Input Channels | 1 |
| Analog Input BW | 2000 MHz |
| Architecture | Pipeline |
| DNL(Max) | 0.95 +/-LSB |
| DNL(Typ) | 0.25 +/-LSB |
| ENOB | 10.5 Bits |
| INL(Max) | 2.5 +/-LSB |
| INL(Typ) | 0.8 +/-LSB |
| Input Buffer | Yes |
| Input Range | 2.2 Vp-p |
| Interface | Parallel LVDS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 80HTQFP: 196 mm2: 14 x 14(HTQFP) PKG |
| Power Consumption(Typ) | 2250 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Resolution | 12 Bits |
| SFDR | 82 dB |
| SINAD | 64.1 dB |
| SNR | 65.3 dB |
| Sample Rate(Max) | 500 MSPS |
生态计划
| RoHS | Compliant |
设计套件和评估模块
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS5474EVM
ADS5474 14-Bit, 400-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS5463EVM
ADS5463 12-Bit, 500-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: ADS54RF63EVM
ADS54RF63 12-Bit, 550-MSPS, RF Sampling Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: THS770006EVM
THS770006 Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
应用须知
- Impact of sampling-clock spurs on ADC performancePDF, 1.2 Mb, 档案已发布: Jul 14, 2009
- Q3 2009 Issue Analog Applications JournalPDF, 2.1 Mb, 档案已发布: Jul 14, 2009
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, 档案已发布: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, 档案已发布: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
- Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
模型线
系列: ADS5463 (3)
- ADS5463IPFP ADS5463IPFPG4 ADS5463IPFPR
制造商分类
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)