Datasheet AD8250 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 10 MHz G = 1, 2, 5, 10 iCMOS Programmable Gain Instrumentation Amplifier |
| 页数 / 页 | 25 / 9 — AD8250. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 1400. 500. 1200. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 927 Kb |
| 文件语言 | 英语 |
AD8250. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 1400. 500. 1200. 400. 1000. 300. U 800. UNI F. E 600. BE 200. M U N. NUM. 100. 200. –120. –90. –60
文件文字版本
AD8250 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted.
1400 500 1200 400 1000 S S IT T N 300 U 800 UNI F OF O R R E 600 B BE 200 M U N NUM 400 100 200 0 0
06 09
–120 –90 –60 –30 0 30 60 90 120
0
–30 –20 –10 0 10 20 30
0 8- 8- 28
CMRR (µV/V) INPUT OFFSET CURRENT (nA)
28 06 06 Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset Current
350 90 80 300 70 250 ) S z 60 T H / 200 V UNI 50 F I (n O G = 1 R RT 150 40 E BE IS G = 2 30 NUM NO 100 G = 5 20 G = 10 50 10
10 0 8- 28 06
0 0 1 10 100 1k 10k 100k –200 –150 –100 –50 0 50 100 150 200
07 0 8-
FREQUENCY (Hz) OFFSET VOLTAGE RTI (µV)
28 06 Figure 7. Typical Distribution of Offset Voltage, VOSI Figure 10. Voltage Spectral Density Noise vs. Frequency
600 500 S IT 400 N U OF 300 R E B M U N 200 100
1
2µV/DIV 1s/DIV
-01
0
88
–30 –20 –10 0 10 20 30
08 0 62 8- 0
INPUT BIAS CURRENT (nA)
28 06 Figure 8. Typical Distribution of Input Bias Current Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. C | Page 8 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide
TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted.
1400 500 1200 400 1000 S S IT T N 300 U 800 UNI F OF O R R E 600 B BE 200 M U N NUM 400 100 200 0 0
06 09
–120 –90 –60 –30 0 30 60 90 120
0
–30 –20 –10 0 10 20 30
0 8- 8- 28
CMRR (µV/V) INPUT OFFSET CURRENT (nA)
28 06 06 Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset Current
350 90 80 300 70 250 ) S z 60 T H / 200 V UNI 50 F I (n O G = 1 R RT 150 40 E BE IS G = 2 30 NUM NO 100 G = 5 20 G = 10 50 10
10 0 8- 28 06
0 0 1 10 100 1k 10k 100k –200 –150 –100 –50 0 50 100 150 200
07 0 8-
FREQUENCY (Hz) OFFSET VOLTAGE RTI (µV)
28 06 Figure 7. Typical Distribution of Offset Voltage, VOSI Figure 10. Voltage Spectral Density Noise vs. Frequency
600 500 S IT 400 N U OF 300 R E B M U N 200 100
1
2µV/DIV 1s/DIV
-01
0
88
–30 –20 –10 0 10 20 30
08 0 62 8- 0
INPUT BIAS CURRENT (nA)
28 06 Figure 8. Typical Distribution of Input Bias Current Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. C | Page 8 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide