Data Manual TCM8030 (Texas Instruments) - 7
| 制造商 | Texas Instruments |
| 描述 | Baseband Processor For Analog Cellular Telephones |
| 页数 / 页 | 91 / 7 — List of Illustrations |
| 文件格式/大小 | PDF / 566 Kb |
| 文件语言 | 英语 |
List of Illustrations
该数据表的模型线
文件文字版本
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List of Illustrations
Figure Title Page 1–1 Functional Block Diagram . 1–3 1–2 Terminal Assignments . 1–4 3–1 Microcontroller Interface Write Timing Diagram . 3–2 3–2 Microcontroller Interface Read Timing Diagram . 3–2 4–1 NBRXLPF Frequency Response . 4–1 4–2 NBRXLPF Eye Pattern . 4–1 4–3 TXBPF Frequency Response . 4–2 4–4 TXBPF Frequency Response . 4–2 4–5 TXDATLPF and TXSUMLPF Combined Response . 4–3 4–6 Eye Pattern for TXDALPF and TXSUMLPF Combined (Narrowband) . 4–3 4–7 TXLPF Frequency Response . 4–4 4–8 TXLPF Frequency Response . 4–4 4–9 TXSATBPF Response Profile . 4–5 4–10 TXSUMLPF Frequency Response . 4–5 4–11 TXSUMLPF Frequency Response . 4–6 5–1 TCM8030 Detailed Functional Block Diagram . 5–2 5–2 Receive Audio Path . 5–4 5–3 Transmit Audio Path . 5–5 5–4 Data Processor Block Diagram . 5–6 5–5 Miscellaneous Circuit Block Diagrams . 5–7 5–6 Clocking Scheme Functional Block Diagram . 5–10 5–7 Power Modes Block Diagram . 5–12 5–8 Summary of TCM8030 Power-Up Events . 5–15 5–9 Microcontroller Interface Write Timing Diagram . 5–24 5–10 Microcontroller Interface Read Timing Diagram . 5–25 vii Document Outline IMPORTANT NOTICE Contents List of Illustrations List of Tables Introduction TCM8030 Features Data Processing Features Audio Processing Features Functional Block Diagram Terminal Assignments Terminal Functions Electrical Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range (se\ e Note 1) Recommended Operating Conditions Electrical Characteristics Over Recommended Range of Supply Voltages an\ d Operating Conditions (unless otherwise noted) Electrical Characteristics Over Recommended Operating Conditions, V=3.0\ V, clocked by a crystal oscillator at 5.12 MHz DIGITAL I/Os, V = 3 V Transmit Path Specifications, V = 2.7 V to 3.3 V MICAMP1 and MICAMP2 Voice and DTMF (V/D) Trim, MIC1 to TXO COMPRESSOR, MIC1 to TXO LIMITER, MIC1 to TXO TXTRIM, MIC1 to TXO Transmit Path, MIC1 to TXO Transmit Data at TXO TX-DAT TRIM at TXO Transmit SAT at TXO SAT TRIM at TXO Receive Path Specifications, V = 2.7 V to 3.3 V, V= 171.2 mVrms RXAMP RXTRIM, RXGAIN to REC1 EXPANDOR, RXGAIN to REC1 Receive Path, RXGAIN to REC1 VOL CTRL, RXGAIN to REC1 LS DRIVER, at RECP and RECN, Input at RECIN Receive Data Detect, V = 3 V Receive SAT Detect Miscellaneous Block Specifications, V = 3 V DD 2.6.1 Digital-to-Analog Converters DAC1, DAC2, and DAC3 TCXO Amplifier IF Amplifier DTMF Generator AMP7 Timing Requirements Over Recommended Ranges of Operating Conditions (s\ ee Figure 3…1) Parameter Measurement Information Typical Characteristics Principles of Operation Overview Receive Audio Path Transmit Audio Path Data Processor Miscellaneous Circuits Clocks Power Modes Total Power-Down Mode Shutdown Mode Idle Mode Tone Mode Full Operation Mode, DTMF TX Off Full Operation Mode, DTMF TX On Independent Circuits Circuit Definitions Transmit Path Audio Processing Functions Receive Path Audio Processing Functions Transmit Path Data Processing Functions Receive Path Data Processing Functions Transmit Path SAT Processing Functions Receive Path SAT Processing Functions Miscellaneous Functions Microcontroller Interface Operation Microcontroller Write Operation Address 00 - Operational Control Word 1 (C1) Address 01 - DCC/SAT/DSAT Control Word (C2) Address 02 - Signal Polarity Selection (C3) Address 03 - Master Power Enable Modes (C4) Address 04 - FOCC/FVC Optional Controls (C5) Address 05 - Interrupt Control Word 1 (IE1) Address 06 - Interrupt Control Word 2 (IE2) Address 08 - Commence TX (TXSTART) Address 09 - Start Watchdog (WDSTART) Address 0A - Abort TX (TXABORT) Address 0B - Clear TX Buffer (TXCLEAR) Address 0C - Restart Frame Sync (FRAMESYNC) Address 0D - Reset (RST) Address 0E - Reset Arbitration (ARBITRST) Address 10 - TX Data Word 0 (TXD0) Address 11 - TX Data Word 1 (TXD1) Address 12 - TX Data Word 2 (TXD2) Address 13 - TX Data Word 3 (TXD3) Address 14 - TX Data Word 4 (TXD4) Addresses 15, 17, 19 - PIO Control Words (PIOC1, PIOC2, PIOC3) Addresses 16, 18, 1A - PIO Output Words (PO1, PO2, PO3) Address 1B - PIO3 Pullup Enable Transistors (PI3PULL) Address 1C - PIO3 Interrupt Control (PI3INT) Address 20 - RXRF Idle Mode Timer (RXRFTIM) Address 21 - Counter/Timer Coef (TIMER) Address 22 - Mismatch Wideband Address 23 - FOCC Dotting Coefficient (FCCDOT) - Wideband Address 24 - FVC Dotting Coefficient (FVCDOT) - Wideband Address 25 - Allowed Narrowband Errors (NBCOEF) - Narrowband Address 26 - SAT Lock Determination (SATCOEF) - Wideband Address 2E - Data Processor Test Control 1 (DTEST1) Address 30 - Auxiliary Power Enable (AUXPE) Register Address 31 - Clock Source Frequency Select (CLKSRC) Address 32 - Receive-Audio Path Configuration (RXCFG) Address 33 - Transmit-Audio Path Configuration (TXCFG) Address 34 - Microphone and TX DTMF Trim (VDTRIM) Address 35 - Limiter Trim (LIMITER) Address 36 - Transmit SAT Trim (SAT TRIM) Address 37 - Transmit Data Trim (TXDATRIM) Address 38 - Transmit Trim (TXTRIM) Address 39 - Receive Trim (RXTRIM) Address 3A - Loudspeaker Volume Control (VOL CTRL) Address 3B - DTMF Control (DTMFCTRL) Address 3C - Analog Test Modes (ATEST) Address 40 - DAC Range Select (DACRANGE) Address 41 - DAC1 Data (DAC1DAT) Address 42 - DAC2 Data (DAC2DAT) Address 43 - DAC3 Data (DAC3DAT) Address 44 - AFC control (AFCCTRL) Read Operation Address 00 - Status Word 1 Register (S1) Address 01 - Status Word 2 Register (S2) Address 05 - Event Register 1 (E1) Address 06 - Event Register 2 (E2) Address 10 - RX Data Word 0 (RXD0) Address 11 - RX Data Word 1 (RXD1) Address 12 - RX Data Word 2 (RXD2) Address 13 - RX Data Word 3 (RXD3) Addresses 16, 18, 1A - PIO Status Words (PI1, PI2, PI3) Address 22 - RX Repeat Count (RXRPT)- Wideband Address 25 - Narrowband Error Rate (NBERRS) Address 43 - AFC Terminal Count MS Byte (AFCIF1) Address 44 - AFC Terminal Count Middle Byte (AFCIF2) Address 45 - AFC Terminal Count Lower Byte (AFCIF3) Event Register 1 (E1) Status Definitions RX data available (E1 bit 1) TX buffer available (E1 bit 1) Arbitration failure (E1 bit 2) TX sequence complete (E1 bit 3) Change of FOCC busy/idle (E1 bit 4) Counter/timer reaches zero state (E1 bit 5) Wideband SAT/Narrowband DSAT changed (E1 bit 6) Event Register 2 (E2) Status Definitions FOCC data changed value (E2 bit 0) FVC dotting detected … wideband (E2 bit 1) FVC Frame Sync achieved (E2 bit 2) Change in Frame Sync (E2 bit 3) Change of RXRF idle mode power savings (E2 bit 4) NRZ error count register (NBERRS) updated (E2 bit 5) PIO3 input port sensed signal (E2 bit 6) AFC has reached terminal count (E2 bit 7)
List of Illustrations
Figure Title Page 1–1 Functional Block Diagram . 1–3 1–2 Terminal Assignments . 1–4 3–1 Microcontroller Interface Write Timing Diagram . 3–2 3–2 Microcontroller Interface Read Timing Diagram . 3–2 4–1 NBRXLPF Frequency Response . 4–1 4–2 NBRXLPF Eye Pattern . 4–1 4–3 TXBPF Frequency Response . 4–2 4–4 TXBPF Frequency Response . 4–2 4–5 TXDATLPF and TXSUMLPF Combined Response . 4–3 4–6 Eye Pattern for TXDALPF and TXSUMLPF Combined (Narrowband) . 4–3 4–7 TXLPF Frequency Response . 4–4 4–8 TXLPF Frequency Response . 4–4 4–9 TXSATBPF Response Profile . 4–5 4–10 TXSUMLPF Frequency Response . 4–5 4–11 TXSUMLPF Frequency Response . 4–6 5–1 TCM8030 Detailed Functional Block Diagram . 5–2 5–2 Receive Audio Path . 5–4 5–3 Transmit Audio Path . 5–5 5–4 Data Processor Block Diagram . 5–6 5–5 Miscellaneous Circuit Block Diagrams . 5–7 5–6 Clocking Scheme Functional Block Diagram . 5–10 5–7 Power Modes Block Diagram . 5–12 5–8 Summary of TCM8030 Power-Up Events . 5–15 5–9 Microcontroller Interface Write Timing Diagram . 5–24 5–10 Microcontroller Interface Read Timing Diagram . 5–25 vii Document Outline IMPORTANT NOTICE Contents List of Illustrations List of Tables Introduction TCM8030 Features Data Processing Features Audio Processing Features Functional Block Diagram Terminal Assignments Terminal Functions Electrical Specifications Absolute Maximum Ratings Over Operating Free-Air Temperature Range (se\ e Note 1) Recommended Operating Conditions Electrical Characteristics Over Recommended Range of Supply Voltages an\ d Operating Conditions (unless otherwise noted) Electrical Characteristics Over Recommended Operating Conditions, V=3.0\ V, clocked by a crystal oscillator at 5.12 MHz DIGITAL I/Os, V = 3 V Transmit Path Specifications, V = 2.7 V to 3.3 V MICAMP1 and MICAMP2 Voice and DTMF (V/D) Trim, MIC1 to TXO COMPRESSOR, MIC1 to TXO LIMITER, MIC1 to TXO TXTRIM, MIC1 to TXO Transmit Path, MIC1 to TXO Transmit Data at TXO TX-DAT TRIM at TXO Transmit SAT at TXO SAT TRIM at TXO Receive Path Specifications, V = 2.7 V to 3.3 V, V= 171.2 mVrms RXAMP RXTRIM, RXGAIN to REC1 EXPANDOR, RXGAIN to REC1 Receive Path, RXGAIN to REC1 VOL CTRL, RXGAIN to REC1 LS DRIVER, at RECP and RECN, Input at RECIN Receive Data Detect, V = 3 V Receive SAT Detect Miscellaneous Block Specifications, V = 3 V DD 2.6.1 Digital-to-Analog Converters DAC1, DAC2, and DAC3 TCXO Amplifier IF Amplifier DTMF Generator AMP7 Timing Requirements Over Recommended Ranges of Operating Conditions (s\ ee Figure 3…1) Parameter Measurement Information Typical Characteristics Principles of Operation Overview Receive Audio Path Transmit Audio Path Data Processor Miscellaneous Circuits Clocks Power Modes Total Power-Down Mode Shutdown Mode Idle Mode Tone Mode Full Operation Mode, DTMF TX Off Full Operation Mode, DTMF TX On Independent Circuits Circuit Definitions Transmit Path Audio Processing Functions Receive Path Audio Processing Functions Transmit Path Data Processing Functions Receive Path Data Processing Functions Transmit Path SAT Processing Functions Receive Path SAT Processing Functions Miscellaneous Functions Microcontroller Interface Operation Microcontroller Write Operation Address 00 - Operational Control Word 1 (C1) Address 01 - DCC/SAT/DSAT Control Word (C2) Address 02 - Signal Polarity Selection (C3) Address 03 - Master Power Enable Modes (C4) Address 04 - FOCC/FVC Optional Controls (C5) Address 05 - Interrupt Control Word 1 (IE1) Address 06 - Interrupt Control Word 2 (IE2) Address 08 - Commence TX (TXSTART) Address 09 - Start Watchdog (WDSTART) Address 0A - Abort TX (TXABORT) Address 0B - Clear TX Buffer (TXCLEAR) Address 0C - Restart Frame Sync (FRAMESYNC) Address 0D - Reset (RST) Address 0E - Reset Arbitration (ARBITRST) Address 10 - TX Data Word 0 (TXD0) Address 11 - TX Data Word 1 (TXD1) Address 12 - TX Data Word 2 (TXD2) Address 13 - TX Data Word 3 (TXD3) Address 14 - TX Data Word 4 (TXD4) Addresses 15, 17, 19 - PIO Control Words (PIOC1, PIOC2, PIOC3) Addresses 16, 18, 1A - PIO Output Words (PO1, PO2, PO3) Address 1B - PIO3 Pullup Enable Transistors (PI3PULL) Address 1C - PIO3 Interrupt Control (PI3INT) Address 20 - RXRF Idle Mode Timer (RXRFTIM) Address 21 - Counter/Timer Coef (TIMER) Address 22 - Mismatch Wideband Address 23 - FOCC Dotting Coefficient (FCCDOT) - Wideband Address 24 - FVC Dotting Coefficient (FVCDOT) - Wideband Address 25 - Allowed Narrowband Errors (NBCOEF) - Narrowband Address 26 - SAT Lock Determination (SATCOEF) - Wideband Address 2E - Data Processor Test Control 1 (DTEST1) Address 30 - Auxiliary Power Enable (AUXPE) Register Address 31 - Clock Source Frequency Select (CLKSRC) Address 32 - Receive-Audio Path Configuration (RXCFG) Address 33 - Transmit-Audio Path Configuration (TXCFG) Address 34 - Microphone and TX DTMF Trim (VDTRIM) Address 35 - Limiter Trim (LIMITER) Address 36 - Transmit SAT Trim (SAT TRIM) Address 37 - Transmit Data Trim (TXDATRIM) Address 38 - Transmit Trim (TXTRIM) Address 39 - Receive Trim (RXTRIM) Address 3A - Loudspeaker Volume Control (VOL CTRL) Address 3B - DTMF Control (DTMFCTRL) Address 3C - Analog Test Modes (ATEST) Address 40 - DAC Range Select (DACRANGE) Address 41 - DAC1 Data (DAC1DAT) Address 42 - DAC2 Data (DAC2DAT) Address 43 - DAC3 Data (DAC3DAT) Address 44 - AFC control (AFCCTRL) Read Operation Address 00 - Status Word 1 Register (S1) Address 01 - Status Word 2 Register (S2) Address 05 - Event Register 1 (E1) Address 06 - Event Register 2 (E2) Address 10 - RX Data Word 0 (RXD0) Address 11 - RX Data Word 1 (RXD1) Address 12 - RX Data Word 2 (RXD2) Address 13 - RX Data Word 3 (RXD3) Addresses 16, 18, 1A - PIO Status Words (PI1, PI2, PI3) Address 22 - RX Repeat Count (RXRPT)- Wideband Address 25 - Narrowband Error Rate (NBERRS) Address 43 - AFC Terminal Count MS Byte (AFCIF1) Address 44 - AFC Terminal Count Middle Byte (AFCIF2) Address 45 - AFC Terminal Count Lower Byte (AFCIF3) Event Register 1 (E1) Status Definitions RX data available (E1 bit 1) TX buffer available (E1 bit 1) Arbitration failure (E1 bit 2) TX sequence complete (E1 bit 3) Change of FOCC busy/idle (E1 bit 4) Counter/timer reaches zero state (E1 bit 5) Wideband SAT/Narrowband DSAT changed (E1 bit 6) Event Register 2 (E2) Status Definitions FOCC data changed value (E2 bit 0) FVC dotting detected … wideband (E2 bit 1) FVC Frame Sync achieved (E2 bit 2) Change in Frame Sync (E2 bit 3) Change of RXRF idle mode power savings (E2 bit 4) NRZ error count register (NBERRS) updated (E2 bit 5) PIO3 input port sensed signal (E2 bit 6) AFC has reached terminal count (E2 bit 7)