Datasheet AD743 (Analog Devices) - 6

制造商Analog Devices
描述Ultralow Noise BiFET Op Amp
页数 / 页13 / 6 — AD743. 100. 3.5. 150. 140. PHASE. 3.0. 130. GAIN. 120. 2.5. SLEW RATE …
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文件语言英语

AD743. 100. 3.5. 150. 140. PHASE. 3.0. 130. GAIN. 120. 2.5. SLEW RATE (V/. OPEN-LOOP GAIN (dB). PHASE MARGIN (Degrees). –20. 2.0. 10k. 100k. 10M. 100M

AD743 100 3.5 150 140 PHASE 3.0 130 GAIN 120 2.5 SLEW RATE (V/ OPEN-LOOP GAIN (dB) PHASE MARGIN (Degrees) –20 2.0 10k 100k 10M 100M

该数据表的模型线

文件文字版本

AD743 100 100 3.5 150 80 80 140 PHASE s) 60 60

3.0 130 40 40 GAIN 120 20 20 2.5 SLEW RATE (V/ OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) PHASE MARGIN (Degrees) 100 0 0 –20 –20 2.0 80 100 1k 10k 100k 1M 10M 100M –60 –40 –20 0 20 40 60 80 100 120 140 0 5 10 15 20 SUPPLY VOLTAGE (

V) FREQUENCY (Hz) TEMPERATURE (

C)
TPC 10. Open-Loop Gain and TPC 11. Slew Rate vs. Temperature TPC 12. Open-Loop Gain vs. Phase vs. Frequency (Gain = –1) Supply Voltage, RLOAD = 2 kΩ
120 120 35 30 100 100 VCM =

10V 25 80 80 R + SUPPLY L = 2k

20 60 60 15 40 40 10 – SUPPLY OUTPUT VOLTAGE (V p-p) 20 20 COMMON-MODE REJECTION (dB) POWER SUPPLY REJECTION (dB) 5 0 0 0 100 1k 10k 100k 1M 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)
TPC 13. Common-Mode TPC 14. Power Supply Rejection TPC 15. Large Signal Frequency Rejection vs. Frequency vs. Frequency Response
) ) –70 Hz 100 1k Hz –80 CLOSED-LOOP GAIN =

1 –90 10 100 –100 GAIN = +10 –110 THD (dB) 10 1 –120 CLOSED-LOOP GAIN =

10 GAIN = –1 –130 –140 1 10 100 1k 10k 100k 0.1 CURRENT NOISE SPECTRAL DENSITY (fA/ 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) VOLTAGE NOISE (PREFERRED TO INPUT) (nV/ FREQUENCY (Hz) FREQUENCY (Hz)
TPC 16. Total Harmonic Distortion TPC 17. Input Voltage Noise TPC 18. Input Current Noise vs. Frequency Spectral Density Spectral Density REV. E –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS CONNECTION DIAGRAMS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD SUSCEPTIBILITY ORDERING GUIDE Typical Performance Characteristics OP AMP PERFORMANCE: JFET VS. BIPOLAR DESIGNING CIRCUITS FOR LOW NOISE LOW NOISE CHARGE AMPLIFIERS HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT REDUCED POWER SUPPLY OPERATION FOR LOWER IB AN INPUT IMPEDANCE COMPENSATED, SALLEN-KEY FILTER TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS LOW NOISE HYDROPHONE AMPLIFIER BALANCING SOURCE IMPEDANCES OUTLINE DIMENSIONS Revision History