Datasheet AD744 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Precision, 500 ns Settling BiFET Op Amp |
| 页数 / 页 | 13 / 8 — AD744. POWER SUPPLY BYPASSING. +VS. 0.1. –VS. MEASURING AD744 SETTLING … |
| 修订版 | D |
| 文件格式/大小 | PDF / 511 Kb |
| 文件语言 | 英语 |
AD744. POWER SUPPLY BYPASSING. +VS. 0.1. –VS. MEASURING AD744 SETTLING TIME. TO TEKTRONIX. +15V. 7A26. 20pF. OSCILLOSCOPE. COM. PREAMP. 5pF
文件文字版本
AD744 POWER SUPPLY BYPASSING
The error signal is thus clamped twice: once to prevent overloading The power supply connections to the AD744 must maintain a amplifier A2 and then a second time to avoid overloading the low impedance to ground over a bandwidth of 10 MHz or more. oscilloscope preamp. A Tektronix oscilloscope preamp type This is especially important when driving a significant resistive 7A26 was carefully chosen because it recovers from the or capacitive load, since all current delivered to the load comes approximately 0.4 V overload quickly enough to allow accurate from the power supplies. Multiple high quality bypass capacitors measurement of the AD744’s 500 ns settling time. Amplifier A2 are recommended for each power supply line in any critical is a very high-speed FET-input op amp; it provides a voltage application. A 0.1 µF ceramic and a 1 µF electrolytic capacitor gain of 10, amplifying the error signal output of the AD744 as shown in Figure 24 placed as close as possible to the ampli- under test. fier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applica- tions. A minimum bypass capacitance of 0.1 µF should be used for any application.
+VS 1
F 0.1
F AD744 1
F 0.1
F –VS
Figure 24. Recommended Power Supply Bypassing Figure 26. Settling Characteristics 0 to +10 V Step Upper Trace: Output of AD744 Under Test (5 V/div.)
MEASURING AD744 SETTLING TIME
Lower Trace: Amplified Error Voltage (0.01%/div.) The photos of Figures 26 and 27 show the dynamic response of the AD744 while operating in the settling time test circuit of Figure 25. The input of the settling time fixture is driven by a flat-top pulse generator. The error signal output from the false summing node of A1, the AD744 under test, is clamped, ampli- fied by op amp A2 and then clamped again.
TO TEKTRONIX +15V +VS 7A26 1M
⍀
20pF OSCILLOSCOPE COM PREAMP 5pF INPUT SECTION –15V –VS (VIA LESS THAN 1 FT 50
⍀
COAXIAL CABLE) V 206
⍀
ERROR
ⴛ
10 2X A2 HP2835 AD3554 2X HP2835 0.47
F +VS –V 0.47
F S
Figure 27. Settling Characteristics 0 to –10 V Step
10k
⍀ Upper Trace: Output of AD744 Under Test (5 V/div.)
1.1k
⍀ Lower Trace: Amplified Error Voltage (0.01%/div.)
0.2pF – 0.8pF NULL 4.99k
⍀
4.99k
⍀
200
⍀
10k
⍀
FLAT-TOP 5pF – 18pF PULSE GENERATOR VIN 10k
⍀
AD744 A1 5k
⍀
10pF DATA DYNAMICS 5109 +VS OR –V EQUIVALENT S 1
F 0.1
F 1
F 0.1
F NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
Figure 25. Settling Time Test Circuit REV. C –7–
The error signal is thus clamped twice: once to prevent overloading The power supply connections to the AD744 must maintain a amplifier A2 and then a second time to avoid overloading the low impedance to ground over a bandwidth of 10 MHz or more. oscilloscope preamp. A Tektronix oscilloscope preamp type This is especially important when driving a significant resistive 7A26 was carefully chosen because it recovers from the or capacitive load, since all current delivered to the load comes approximately 0.4 V overload quickly enough to allow accurate from the power supplies. Multiple high quality bypass capacitors measurement of the AD744’s 500 ns settling time. Amplifier A2 are recommended for each power supply line in any critical is a very high-speed FET-input op amp; it provides a voltage application. A 0.1 µF ceramic and a 1 µF electrolytic capacitor gain of 10, amplifying the error signal output of the AD744 as shown in Figure 24 placed as close as possible to the ampli- under test. fier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applica- tions. A minimum bypass capacitance of 0.1 µF should be used for any application.
+VS 1
F 0.1
F AD744 1
F 0.1
F –VS
Figure 24. Recommended Power Supply Bypassing Figure 26. Settling Characteristics 0 to +10 V Step Upper Trace: Output of AD744 Under Test (5 V/div.)
MEASURING AD744 SETTLING TIME
Lower Trace: Amplified Error Voltage (0.01%/div.) The photos of Figures 26 and 27 show the dynamic response of the AD744 while operating in the settling time test circuit of Figure 25. The input of the settling time fixture is driven by a flat-top pulse generator. The error signal output from the false summing node of A1, the AD744 under test, is clamped, ampli- fied by op amp A2 and then clamped again.
TO TEKTRONIX +15V +VS 7A26 1M
⍀
20pF OSCILLOSCOPE COM PREAMP 5pF INPUT SECTION –15V –VS (VIA LESS THAN 1 FT 50
⍀
COAXIAL CABLE) V 206
⍀
ERROR
ⴛ
10 2X A2 HP2835 AD3554 2X HP2835 0.47
F +VS –V 0.47
F S
Figure 27. Settling Characteristics 0 to –10 V Step
10k
⍀ Upper Trace: Output of AD744 Under Test (5 V/div.)
1.1k
⍀ Lower Trace: Amplified Error Voltage (0.01%/div.)
0.2pF – 0.8pF NULL 4.99k
⍀
4.99k
⍀
200
⍀
10k
⍀
FLAT-TOP 5pF – 18pF PULSE GENERATOR VIN 10k
⍀
AD744 A1 5k
⍀
10pF DATA DYNAMICS 5109 +VS OR –V EQUIVALENT S 1
F 0.1
F 1
F 0.1
F NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
Figure 25. Settling Time Test Circuit REV. C –7–