Datasheet AD654 (Analog Devices) - 10

AD654 5V GND FREQUENCY DOUBLING
Since the AD654’s output is a square-wave rather than a pulse train, information about the input signal is carried on both
20pF VCC VDD VSS P10
halves of the output waveform. The circuit in Figure 12 converts
XTAL1 PORT 1
the output into a pulse train, effectively doubling the output
6MHz 20pF P17
frequency, while preserving the better low frequency linearity of
XTAL2 1
m
F P20
the AD654. This circuit also accommodates an input voltage
RESET
that is greater than the AD654 supply voltage.
PORT 2 EA 8048
Resistors R1–R3 are used to scale the 0 V to +10 V input voltage
NC SS P27
down to 0 V to +1 V as seen at Pin 4 of the AD654. Recall that
INT DB0
VIN must be less than VSUPPLY –4 V, or in this case less than 1 V.
T0 BUS
The timing resistor and capacitor are selected such that this 0 V
PORT T1 DB7
to +1 V signal seen at Pin 4 results in a 0 kHz to 200 kHz output
ALE PSEN PROG WR RD
frequency.
NC NC
The use of R4, C1 and the XOR gate doubles this 200 kHz
5V NC = NO CONNECT
output frequency to 400 kHz. The AD654 output transistor is
10k
V basically used as a switch, switching capacitor C1 between a charging mode and a discharging mode of operation. The voltages
1 8
seen at the input of the 74LS86 are shown in the waveform dia-
2 7 AD654 1000pF
gram. Due to the difference in the charge and discharge time
3 6
constants, the output pulse widths of the 74LS86 are not equal.
1k
V
+ 4 5
The output pulse is wider when the capacitor is charging due to its longer rise time than fall time. The pulses should therefore be
V 825
V
IN 1%
counted on their rising, rather than falling, edges.
(0V TO 1V) 500
V
– D A
Figure 11. AD654 VFC as an ADC
5V RPU 2.87k
V
74LS86 A AD654 C R1 R2 8.06k
V
2k
V
OSC/ R4 DRIVER 1k
V
B C1 1000pF R3 V/F OUTPUT VIN 1k
V
FS = 400MHz (0V TO 10V) RT 1k
V
CT 500pF OFF TRANSISTOR ON V A 0 V B 0 5 C 0 WAVEFORM DIAGRAM
Figure 12. Frequency Doubler REV. C –9–