Datasheet ATtiny4, ATtiny5, ATtiny9, ATiny10. Summary Datasheet (Microchip) - 4
| 制造商 | Microchip |
| 描述 | Atmel 8-bit AVR Microcontroller with 512/1024 Bytes In-System Programmable Flash |
| 页数 / 页 | 17 / 4 — Pin Configurations Figure 1-1. Pinout of ATtiny4/5/9/10. 1.1. Pin … |
| 文件格式/大小 | PDF / 341 Kb |
| 文件语言 | 英语 |
Pin Configurations Figure 1-1. Pinout of ATtiny4/5/9/10. 1.1. Pin Descriptions. 1.1.1. VCC. 1.1.2. GND. 1.1.3. Port B (PB[3:0]). 1.1.4
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文件文字版本
1. Pin Configurations Figure 1-1. Pinout of ATtiny4/5/9/10
SOT-23 (PCINT0/TPIDATA /OC0A/ADC0/AIN0) PB0 1 6 PB3 (RESET/PCINT3/ADC3) GND 2 5 VCC (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 3 4 PB2 (T0/CLKO/PCINT2/INT0/ADC2) UDFN (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1 8 PB2 (T0/CLKO/PCINT2/INT0/ADC2) NC 2 7 VCC NC 3 6 PB3 (RESET/PCINT3/ADC3) GND 4 5 PB0 (AIN0/ADC0/OC0A/TPIDATA /PCINT0) Power Digital Analog Clock GND NC
1.1. Pin Descriptions 1.1.1. VCC
Digital supply voltage.
1.1.2. GND
Ground.
1.1.3. Port B (PB[3:0])
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
1.1.4. RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in System and Reset Characteristics of Electrical Characteristics. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATiny10 [DATASHEET] 4 Atmel-8127H-ATiny4/ ATiny5 /ATiny9/ ATiny10_Datasheet_Summary-11/2016 Document Outline Introduction Feature Table of Contents 1. Pin Configurations 1.1. Pin Descriptions 1.1.1. VCC 1.1.2. GND 1.1.3. Port B (PB[3:0]) 1.1.4. RESET 2. Ordering Information 2.1. ATtiny4 2.2. ATtiny5 2.3. ATtiny9 2.4. ATtiny10 3. Overview 3.1. Block Diagram 3.1.1. Description 3.2. Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 4. General Information 4.1. Resources 4.2. Data Retention 4.3. About Code Examples 4.4. Capacitive Touch Sensing 4.4.1. QTouch Library 5. Packaging Information 5.1. 6ST1 5.2. 8MA4 6. Errata 6.1. ATtiny4 6.1.1. Rev. E 6.1.2. Rev. D 6.1.3. Rev. A – C 6.2. ATtiny5 6.2.1. Rev. E 6.2.2. Rev. D 6.2.3. Rev. A – C 6.3. ATtiny9 6.3.1. Rev. E 6.3.2. Rev. D 6.3.3. Rev. A – C 6.4. ATtiny10 6.4.1. Rev. E 6.4.2. Rev. C – D 6.4.3. Rev. A – B
SOT-23 (PCINT0/TPIDATA /OC0A/ADC0/AIN0) PB0 1 6 PB3 (RESET/PCINT3/ADC3) GND 2 5 VCC (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 3 4 PB2 (T0/CLKO/PCINT2/INT0/ADC2) UDFN (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1 8 PB2 (T0/CLKO/PCINT2/INT0/ADC2) NC 2 7 VCC NC 3 6 PB3 (RESET/PCINT3/ADC3) GND 4 5 PB0 (AIN0/ADC0/OC0A/TPIDATA /PCINT0) Power Digital Analog Clock GND NC
1.1. Pin Descriptions 1.1.1. VCC
Digital supply voltage.
1.1.2. GND
Ground.
1.1.3. Port B (PB[3:0])
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
1.1.4. RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in System and Reset Characteristics of Electrical Characteristics. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. Atmel ATtiny4 / ATtiny5 / ATtiny9 / ATiny10 [DATASHEET] 4 Atmel-8127H-ATiny4/ ATiny5 /ATiny9/ ATiny10_Datasheet_Summary-11/2016 Document Outline Introduction Feature Table of Contents 1. Pin Configurations 1.1. Pin Descriptions 1.1.1. VCC 1.1.2. GND 1.1.3. Port B (PB[3:0]) 1.1.4. RESET 2. Ordering Information 2.1. ATtiny4 2.2. ATtiny5 2.3. ATtiny9 2.4. ATtiny10 3. Overview 3.1. Block Diagram 3.1.1. Description 3.2. Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 4. General Information 4.1. Resources 4.2. Data Retention 4.3. About Code Examples 4.4. Capacitive Touch Sensing 4.4.1. QTouch Library 5. Packaging Information 5.1. 6ST1 5.2. 8MA4 6. Errata 6.1. ATtiny4 6.1.1. Rev. E 6.1.2. Rev. D 6.1.3. Rev. A – C 6.2. ATtiny5 6.2.1. Rev. E 6.2.2. Rev. D 6.2.3. Rev. A – C 6.3. ATtiny9 6.3.1. Rev. E 6.3.2. Rev. D 6.3.3. Rev. A – C 6.4. ATtiny10 6.4.1. Rev. E 6.4.2. Rev. C – D 6.4.3. Rev. A – B