Datasheet PIC10F220, PIC10F222 (Microchip) - 10

PIC10F220/222 NOTES:
DS40001270F-page 8  2005-2013 Microchip Technology Inc. Document Outline Device Included In This Data Sheet: High-Performance RISC CPU: Special Microcontroller Features: Low-Power Features/CMOS Technology: Peripheral Features: 6-Lead SOT-23 Pin Diagram 8-Lead DIP Pin Diagram 8-Lead DFN Pin Diagram Table of Contents Most Current Data Sheet Errata Customer Notification System 1.0 General Description 1.1 Applications TABLE 1-1: PIC10F220/222 Devices(1), (2) 2.0 Device Varieties 2.1 Quick Turn Programming (QTP) Devices 2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices 3.0 Architectural Overview FIGURE 3-1: Block Diagram TABLE 3-1: Pinout Description 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining FIGURE 3-2: Clock/Instruction Cycle EXAMPLE 3-1: Instruction Pipeline Flow 4.0 Memory Organization 4.1 Program Memory Organization for the PIC10F220 FIGURE 4-1: Program Memory Map and Stack for the PIC10F220 4.2 Program Memory Organization for the PIC10F222 FIGURE 4-2: Program Memory Map and Stack for the PIC10F222 4.3 Data Memory Organization FIGURE 4-3: PIC10F220 Register File Map FIGURE 4-4: PIC10F222 Register File Map TABLE 4-1: Special Function Register (SFR) Summary 4.4 STATUS Register Register 4-1: Status Register (Address: 03h) 4.5 OPTION Register Register 4-2: Option Register 4.6 OSCCAL Register Register 4-3: OSCCAL – Oscillator Calibration Register (Address: 05h) 4.7 Program Counter FIGURE 4-5: Loading of PC Branch Instructions 4.8 Stack 4.9 Indirect Data Addressing; INDF and FSR Registers EXAMPLE 4-1: How to Clear RAM Using Indirect Addressing FIGURE 4-6: Direct/Indirect Addressing 5.0 I/O Port 5.1 GPIO 5.2 TRIS Registers 5.3 I/O Interfacing FIGURE 5-1: Equivalent Circuit for a Single I/O Pin TABLE 5-1: Order of Precedence for Pin Functions TABLE 5-2: Requirements to Make Pins Available in Digital Mode FIGURE 5-2: Block Diagram of GP0 and GP1 FIGURE 5-3: Block Diagram of GP2 FIGURE 5-4: Block Diagram of GP3 TABLE 5-3: Summary of Port Registers 5.4 I/O Programming Considerations EXAMPLE 5-1: I/O Port Read-modify- write Instructions FIGURE 5-5: Successive I/O Operation 6.0 TMR0 Module and TMR0 Register FIGURE 6-1: TIMER0 Block Diagram FIGURE 6-2: TIMER0 Timing: Internal Clock/No Prescale FIGURE 6-3: TIMER0 Timing: Internal Clock/Prescale 1:2 TABLE 6-1: Registers Associated With TIMER0 6.1 Using Timer0 With An External Clock FIGURE 6-4: TIMER0 Timing with External Clock 6.2 Prescaler EXAMPLE 6-1: Changing Prescaler (TIMER0 ® WDT) EXAMPLE 6-2: Changing Prescaler (WDT®TIMER0) FIGURE 6-5: Block Diagram of the TIMER0/WDT Prescaler 7.0 Analog-to-Digital (A/D) converter 7.1 Clock Divisors 7.2 Voltage Reference 7.3 Analog Mode Selection 7.4 A/D Converter Channel Selection 7.5 The GO/DONE bit 7.6 Sleep TABLE 7-1: Effects of Sleep and Wake on ADCON0 7.7 Analog Conversion Result Register 7.8 Internal Absolute Voltage Reference Register 7-1: ADCON0: A/D Converter 0 Register Register 7-2: Adres: Analog Conversion Result Register 7.9 A/D Acquisition Requirements EQUATION 7-1: Acquisition Time Example FIGURE 7-1: aNALOG iNPUT mODULE 8.0 Special Features Of The CPU 8.1 Configuration Bits Register 8-1: CONFIG: Configuration Word(1) 8.2 Oscillator Configurations 8.3 Reset TABLE 8-1: Reset Conditions for Registers – PIC10F220/222 TABLE 8-2: Reset Condition for Special Registers FIGURE 8-1: MCLR Select 8.4 Power-on Reset (POR) FIGURE 8-2: Simplified Block Diagram of On-chip Reset Circuit FIGURE 8-3: Time-out Sequence on Power-up (MCLR Pulled Low) FIGURE 8-4: Time-out Sequence on Power-up (MCLR Tied To Vdd): Fast Vdd Rise Time FIGURE 8-5: Time-Out Sequence on Power-Up (MCLR Tied to Vdd): Slow Vdd Rise Time 8.5 Device Reset Timer (DRT) TABLE 8-3: DRT (Device Reset Timer Period) 8.6 Watchdog Timer (WDT) FIGURE 8-6: Watchdog Timer Block Diagram TABLE 8-4: Summary of Registers Associated with the Watchdog Timer 8.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO/PD/GPWUF/CWUF) TABLE 8-5: TO/PD/GPWUF Status After Reset 8.8 Reset on Brown-out FIGURE 8-7: Brown-out Protection Circuit 1 FIGURE 8-8: Brown-out Protection Circuit 2 FIGURE 8-9: Brown-out Protection Circuit 3 8.9 Power-down Mode (Sleep) 8.10 Program Verification/Code Protection 8.11 ID Locations 8.12 In-Circuit Serial Programming™ FIGURE 8-10: Typical In-Circuit Serial Programming™ Connection 9.0 Instruction Set Summary TABLE 9-1: Opcode Field Descriptions FIGURE 9-1: General Format for Instructions TABLE 9-2: Instruction Set Summary 9.1 Instruction Description 10.0 Electrical Characteristics Absolute Maximum Ratings(†) FIGURE 10-1: Voltage-Frequency Graph, -40°C £ ta £ +125°C 10.1 DC Characteristics: PIC10F220/222 (Industrial) 10.2 DC Characteristics: PIC10F220/222 (Extended) 10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended) TABLE 10-1: Pull-up Resistor Ranges 10.4 Timing Parameter Symbology and Load Conditions FIGURE 10-2: Load Conditions TABLE 10-2: Calibrated Internal RC Frequencies – PIC10F220/222 FIGURE 10-3: Reset, Watchdog Timer and Device Reset Timer Timing TABLE 10-3: Reset, Watchdog Timer and Device Reset Timer – PIC10F220/222 FIGURE 10-4: Timer0 Clock Timings TABLE 10-4: Timer0 Clock Requirements TABLE 10-5: A/D Converter Characteristics TABLE 10-6: A/D Conversion Requirements 11.0 DC and AC Characteristics Graphs and Tables. FIGURE 11-1: Idd vs. Vdd Over Fosc (4 MHz) FIGURE 11-2: Idd vs. Vdd Over Fosc (8 MHz) FIGURE 11-3: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled) FIGURE 11-4: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled) FIGURE 11-5: Typical WDT Ipd VS. Vdd FIGURE 11-6: Maximum WDT Ipd VS. Vdd Over Temperature FIGURE 11-7: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler) FIGURE 11-8: Vol VS. Iol Over Temperature (Vdd = 3.0V) FIGURE 11-9: Vol VS. Iol Over Temperature (Vdd = 5.0V) FIGURE 11-10: Voh VS. Ioh Over Temperature (Vdd = 3.0V) FIGURE 11-11: Voh VS. Ioh Over Temperature (Vdd = 5.0V) FIGURE 11-12: TTL Input Threshold Vin VS. Vdd FIGURE 11-13: Schmitt Trigger Input Threshold Vin VS. Vdd 12.0 Development Support 12.1 MPLAB X Integrated Development Environment Software 12.2 MPLAB XC Compilers 12.3 MPASM Assembler 12.4 MPLINK Object Linker/ MPLIB Object Librarian 12.5 MPLAB Assembler, Linker and Librarian for Various Device Families 12.6 MPLAB X SIM Software Simulator 12.7 MPLAB REAL ICE In-Circuit Emulator System 12.8 MPLAB ICD 3 In-Circuit Debugger System 12.9 PICkit 3 In-Circuit Debugger/ Programmer 12.10 MPLAB PM3 Device Programmer 12.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 12.12 Third-Party Development Tools 13.0 Packaging Information 13.1 Package Marking Information TABLE 13-1: 8-Lead 2X3 dfn (mc) tOP mARKINg TABLE 13-2: 6-Lead SOT-23 (OT) Package tOP mARKINg Appendix A: Revision History INDEX The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales